Acer Aspire 5741_Compal_LA-5892P_NEW70_80_90_50_PEW51_Rev1.0.pdf

(1089 KB) Pobierz
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Compal Confidential
2
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NEW70 / 80 / 90 / 50 <LA-5892P> M/B Schematics Document
PEW51 <LA-5892P> M/B Schematics Document
Intel Arrandale Processor with DDRIII + Ibex Peak-M
3
2010-06-09
REV:1.0
3
4
4
Security Classification
Issued Date
2009/5/12
Compal Secret Data
Deciphered Date
2010/04/15
Title
Compal Electronics, Inc.
SCHEMATICS,MB A5892
Rev
C
Sheet
E
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401826
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Tuesday, June 22, 2010
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Compal Confidential
Model Name NEW70 / 80 / 90 / 50
File Name : LA-5892P
1
ZZZ
DAZ0C900200
PCB NEW70 LA-5892P
46@
ZZZ1
RO0000003HM
HDMI+HDCP LOGO
1
Fan Control
page 26
Intel
Arrandale (UMA)
Processor
rPGA988A
page 4,5,6,7,8,9
Memory BUS(DDRIII)
204pin DDRIII-SO-DIMM X2
Dual Channel
BANK 0, 1, 2, 3
1.5V DDRIII 800/1066/1333
6.4G/8.5G/10.6G
100M/133M/166M(CFD)
page 10,11
USB conn x3
USB port 0 (sub board)
USB Port 1 Left side
USB port 2 (sub board)
page 39
FDI x8
(UMA)
100MHz
2.7GT/s
2
DMI x4
100MHz
1GB/s x4
Bluetooth
Conn
USB port 11
page 29
CMOS
Camera
USB port 8
page 22
Mini card
USB port 12
USB port 13
page 39
Card
Reader
USB port 9
page 39
2
LVDS Conn.
CRT Conn.
page 22
page 23
LVDS(UMA)
CRT(UMA)
USBx14
3.3V 48MHz
HDMI Conn.
page 24
Level Shift
page 24
HDMI(UMA)
port 2,4
port 1
Intel
Ibex Peak-M
page 13,14,15,16,17
18,19,20,21
HD Audio
3.3V 24MHz
PCI-Express x 8 (ABD PCIE1 2.5GT/S CKD PCIE1/2 2.5/5GT/S)
100MHz
PCH
SATA x 6 (GEN1 1.5GT/S ,GEN2 3GT/S)
100MHz
HDA Codec
SPI
port 0
port 1
SATA ODD
Conn.
page 25
ALC888
page 33
MINI Card x2
WLAN, 3G
page 26
LAN(GbE)
BCM57780
page 27
SPI ROM x2
page 13
SATA HDD
Conn.
page 25
Audio AMP
APA2051
page 34
3
RJ45
page 28
LPC BUS
33MHz
3
Int. Speaker
page 34
RTC CKT.
Power ON/Off CKT.
DC/DC Interface CKT.
Power Circuit DC/DC CKT.
LS-5891P
LS-5892P
Touch Pad
LS-5893P
LS-5894P
LS-5895P
ENE KB926
page 30
Int.KBD
page 31
Clock Generator
IDT: 9LRS3199AKLFT
SILEGO: SLG8SP587
133/120/100/96/14.318MHZ to PCH
48MHZ to CardReader
page 12
page 31
BIOS ROM
page 31
4
4
Security Classification
Issued Date
2009/5/12
Compal Secret Data
Deciphered Date
2010/04/15
Title
Compal Electronics, Inc.
SCHEMATICS,MB A5892
Document Number
Rev
C
Sheet
E
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
C
D
401826
Tuesday, June 22, 2010
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STATE
SIGNAL
SLP_S1# SLP_S3# SLP_S4# SLP_S5#
HIGH
LOW
LOW
LOW
LOW
HIGH
HIGH
LOW
LOW
LOW
HIGH
HIGH
HIGH
LOW
LOW
HIGH
HIGH
HIGH
HIGH
LOW
+VALW
ON
ON
ON
ON
ON
+V
ON
ON
ON
OFF
OFF
+VS
ON
ON
OFF
OFF
OFF
Clock
ON
LOW
OFF
OFF
OFF
1
Voltage Rails
Power Plane
VIN
B+
1
Full ON
Description
Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU
0.75V switched power rail for DDR terminator
1.05V switched power rail for PCH
1.05V switched power rail (1.05 for AUB CPU)
1.5V power rail for DDRIII
1.5V switched power rail
1.8V switched power rail
3.3V always on power rail
3.3V power rail for LAN
3.3V switched power rail
5V always on power rail
5V switched power rail
5V power rail for PCH
VSB always on power rail
RTC power
S1
N/A
N/A
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
S3
N/A
N/A
ON
OFF
OFF
OFF
ON
OFF
OFF
ON
ON
OFF
ON
OFF
ON
ON
ON
S5
N/A
N/A
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON*
ON*
OFF
ON*
OFF
ON
ON*
ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
+CPU_CORE
+0.75VS
+1.05VS
+1.05VS_VTT
+1.5V
+1.5VS
+1.8VS
+3VALW
+3V_LAN
+3VS
+5VALW
+5VS
+5V
+VSB
+RTCVCC
Project ID / Board ID Table for EC-AD channel
Vcc
Ra/Rc
0
1
2
3
4
5
6
7
3.3V +/- 5%
100K +/- 5%
Rb / Rd
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
NC
V
AD_BID
min
0 V
0.216 V
0.436 V
0.712 V
1.036 V
1.453 V
1.935 V
2.500 V
V
AD_BID
typ
0 V
0.250 V
0.503 V
0.819 V
1.185 V
1.650 V
2.200 V
3.300 V
BOM Config
V
AD_BID
max
0 V
0.289 V
0.538 V
0.875 V
1.264 V
1.759 V
2.341 V
3.300 V
Board ID
0.1
0.2
0.3
1.0
Project ID
NEWX0
PEW51
2
2
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
BTO Option Table
BTO Item
HDMI
3G
9050@
7080@
For NEWX0 ID
For PEW51 ID
BOM Structure
HDMI@
3G@
NEW90 / NEW50
NEW70 / NEW80
NEWX0@
PEW51@
External PCI Devices
Device
IDSEL#
REQ#/GNT#
Interrupts
EC SM Bus1 address
Device
Smart Battery
EC SM Bus2 address
Device
Address
Address
0001 011X b
Ibex SM Bus address
3
USB Port Table
USB 2.0 USB 1.1 Port
UHCI0
UHCI1
EHCI1
UHCI2
UHCI3
UHCI4
EHCI2
UHCI5
UHCI6
3
4
5
6
7
8
9
10
11
12
13
Camera
Card Reader
SIM CARD
Blue Tooth
1st Min-Card
2st Min-Card
Compal Secret Data
2009/08/01
Deciphered Date
2010/08/01
Title
Device
Clock Generator
(9LRS3199AKLFT, SLG8SP587)
DDR DIMM0
DDR DIMM2
Address
1101 0010b
1001 000Xb
1001 010Xb
0
1
2
4 External
USB Port
Ext1 USB
Ext3 HS USB
Ext2 USB
3 External
USB Port
Ext1 USB
Ext3 HS USB
Ext2 USB
3
4
Camera
Card Reader
SIM CARD
Blue Tooth
1st Min-Card
2st Min-Card
4
Security Classification
Issued Date
Compal Electronics, Inc.
SCHEMATICS,MB A5892
Document Number
Rev
C
Sheet
E
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401826
Tuesday, June 22, 2010
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1
JCPU1E
JCPU1A
DMI_PTX_HRX_N0
DMI_PTX_HRX_N1
DMI_PTX_HRX_N2
DMI_PTX_HRX_N3
DMI_PTX_HRX_P0
DMI_PTX_HRX_P1
DMI_PTX_HRX_P2
DMI_PTX_HRX_P3
DMI_HTX_PRX_N0
DMI_HTX_PRX_N1
DMI_HTX_PRX_N2
DMI_HTX_PRX_N3
DMI_HTX_PRX_P0
DMI_HTX_PRX_P1
DMI_HTX_PRX_P2
DMI_HTX_PRX_P3
PEG_IRCOMP
EXP_RBIAS
A24
C23
B22
A21
B24
D23
B23
A22
D24
G24
F23
H23
D25
F24
E23
G23
DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]
DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]
DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]
DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RBIAS
PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
B26
A26
B27
A25
K35
J34
J33
G35
G32
F34
F31
D35
E33
C33
D32
B32
C31
B28
B30
A31
J35
H34
H33
F35
G33
E34
F32
D34
F33
B33
D31
A32
C30
A28
B29
A30
L33
M35
M33
M30
L31
K32
M29
J31
K29
H30
H29
F29
E28
D29
D27
C26
L34
M34
M32
L30
M31
K31
M28
H31
K28
G30
G29
F28
E27
D28
C27
C25
1
R1
1
R3
2
49.9_0402_1%
2
750_0402_1%
AP25
AL25
AL24
AL22
AJ33
AG9
M27
L28
J17
H17
G25
G17
E31
E30
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
SA_DIMM_VREF
(CFD Only)
SB_DIMM_VREF
(CFD Only)
RSVD11
RSVD12
RSVD13
RSVD14
RSVD32
RSVD33
RSVD34
RSVD35
RSVD36
RSVD_NCTF_37
RSVD38
RSVD39
AJ13
AJ12
AH25
AK26
AL26
AR2
AJ26
AJ27
DMI
DMI
D
D
RSVD_NCTF_40
RSVD_NCTF_41
RSVD_NCTF_42
RSVD_NCTF_43
AP1
AT2
AT3
AR1
R5
3.01K_0402_1%
R6
3.01K_0402_1%
R7
3.01K_0402_1%
R8
3.01K_0402_1%
1
@
1
@
1
@
1
@
2
2
2
2
CFG0
CFG3
CFG4
CFG7
PCI EXPRESS -- GRAPHICS
C
H_FDI_TXP0
H_FDI_TXP1
H_FDI_TXP2
H_FDI_TXP3
H_FDI_TXP4
H_FDI_TXP5
H_FDI_TXP6
H_FDI_TXP7
<15> H_FDI_FSYNC0
<15> H_FDI_FSYNC1
<15> H_FDI_INT
<15> H_FDI_LSYNC0
<15> H_FDI_LSYNC1
D22
C21
D20
C18
G22
E20
F20
G19
F17
E17
C17
F18
D17
FDI_TX[0]
FDI_TX[1]
FDI_TX[2]
FDI_TX[3]
FDI_TX[4]
FDI_TX[5]
FDI_TX[6]
FDI_TX[7]
FDI_FSYNC[0]
FDI_FSYNC[1]
FDI_INT
FDI_LSYNC[0]
FDI_LSYNC[1]
WW41 Recommend not pull down
PCIE2.0 Jitter is over on ES1
RESERVED
H_FDI_TXN0
H_FDI_TXN1
H_FDI_TXN2
H_FDI_TXN3
H_FDI_TXN4
H_FDI_TXN5
H_FDI_TXN6
H_FDI_TXN7
E22
D21
D19
D18
G21
E19
F21
G18
FDI_TX#[0]
FDI_TX#[1]
FDI_TX#[2]
FDI_TX#[3]
FDI_TX#[4]
FDI_TX#[5]
FDI_TX#[6]
FDI_TX#[7]
AM30
AM28
AP31
AL32
AL30
AM31
AN29
AM32
AK32
AK31
AK28
AJ28
AN30
AN32
AJ32
AJ29
AJ30
AK30
H16
CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
RSVD_TP_86
RSVD45
RSVD46
RSVD47
RSVD48
RSVD49
RSVD50
RSVD51
RSVD52
RSVD53
RSVD_NCTF_54
RSVD_NCTF_55
RSVD_NCTF_56
RSVD_NCTF_57
RSVD58
RSVD_TP_59
RSVD_TP_60
KEY
RSVD62
RSVD63
RSVD64
RSVD65
AL28
AL29
AP30
AP32
AL27
AT31
AT32
AP33
AR33
AT33
AT34
AP35
AR35
AR32
E15
F15
A2
D15
C15
AJ15
AH15
Intel(R) FDI
Intel(R) FDI
C
R11
0_0402_5%
@
1
2
@
1
2
R12
0_0402_5%
B19
A19
H_RSVD17_R
H_RSVD18_R
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD_TP_66
RSVD_TP_67
RSVD_TP_68
RSVD_TP_69
RSVD_TP_70
RSVD_TP_71
RSVD_TP_72
RSVD_TP_73
RSVD_TP_74
RSVD_TP_75
RSVD_TP_76
RSVD_TP_77
RSVD_TP_78
RSVD_TP_79
RSVD_TP_80
RSVD_TP_81
RSVD_TP_82
RSVD_TP_83
RSVD_TP_84
RSVD_TP_85
VSS
R9
0_0402_5%
RSVD64_R
2
@
@
RSVD65_R
2
R10
0_0402_5%
1
1
A20
B20
U9
T9
AC9
AB9
DMI_PTX_HRX_N[0..3] <15>
DMI_PTX_HRX_P[0..3] <15>
DMI_HTX_PRX_N[0..3] <15>
DMI_HTX_PRX_P[0..3] <15>
H_FDI_TXN[0..7]
H_FDI_TXP[0..7]
<15>
<15>
C1
A3
RSVD_NCTF_23
RSVD_NCTF_24
AA5
AA4
R8
AD3
AD2
AA2
AA1
R9
AG7
AE3
V4
V5
N2
AD5
AD7
W3
W2
N3
AE5
AD9
AP34
B
J29
J28
A34
A33
C35
B35
RSVD26
RSVD27
RSVD_NCTF_28
RSVD_NCTF_29
RSVD_NCTF_30
RSVD_NCTF_31
B
IC,AUB_CFD_rPGA,R1P0
CONN@
IC,AUB_CFD_rPGA,R1P0
CONN@
A
eDP Signals Mapping
eDP Singal
PEG Singals
PEG_HTX_C_GRX_P15
eDP_TX0
eDP_TX#0 PEG_HTX_C_GRX_N15
eDP_TX1
PEG_HTX_C_GRX_P14
eDP_TX#1 PEG_HTX_C_GRX_N14
eDP_TX2
PEG_HTX_C_GRX_P13
eDP_TX#2 PEG_HTX_C_GRX_N13
PEG_HTX_C_GRX_P12
eDP_TX3
eDP_TX#3 PEG_HTX_C_GRX_N12
eDP_AUX
PEG_GTX_C_HRX_P13
eDP_AUX# PEG_GTX_C_HRX_N13
eDP_HPD# PEG_GTX_C_HRX_P12
5
CFG0 - PCI-Express Configuration Select
CFG4 - Display Port Presence
*1:Disabled; No Physical Display Port
attached to Embedded Display Port
0:Enabled; An external Display Port
device is connected to the Embedded
Display Port
*:Default
A
Lane Reversal
PEG_HTX_C_GRX_P0
PEG_HTX_C_GRX_N0
PEG_HTX_C_GRX_P1
PEG_HTX_C_GRX_N1
PEG_HTX_C_GRX_P2
PEG_HTX_C_GRX_N2
PEG_HTX_C_GRX_P3
PEG_HTX_C_GRX_N3
PEG_GTX_C_HRX_P2
PEG_GTX_C_HRX_N2
PEG_GTX_C_HRX_P3
4
*1:Single PEG
0:Bifurcation enabled
CFG3 - PCI-Express Static Lane Reversal
*1 :Normal Operation
0 :Lane Numbers Reversed
15 -> 0, 14 -> 1, ...
Security Classification
Issued Date
2009/08/01
Compal Secret Data
Deciphered Date
2010/08/01
Title
Compal Electronics, Inc.
SCHEMATICS,MB A5892
Document Number
Rev
C
Sheet
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
401826
Tuesday, June 22, 2010
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5
4
3
2
1
JCPU1B
R18
R19
R20
R21
2
2
2
2
1
20_0402_1%
1
20_0402_1%
1
49.9_0402_1%
1
49.9_0402_1%
@
H_COMP3
H_COMP2
H_COMP1
H_COMP0
SKTOCC#_R
H_CATERR#
AT23
AT24
G16
AT26
AH24
AK14
COMP3
COMP2
COMP1
COMP0
SKTOCC#
CATERR#
BCLK
BCLK#
A16
B16
AR30
AT30
E16
D16
A18
A17
CLK_CPU_XDP
CLK_CPU_XDP#
CLK_CPU_BCLK <18>
CLK_CPU_BCLK# <18>
CLOCKS
MISC
MISC
BCLK_ITP
BCLK_ITP#
PEG_CLK
PEG_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
CLK_CPU_DMI <14>
CLK_CPU_DMI# <14>
CLK_CPU_DP <14>
CLK_CPU_DP# <14>
+1.05VS_VTT
D
T24 PAD
D
THERMAL
THERMAL
<18> H_PECI
R26
1
0_0402_5%
2
H_PECI_R
AT15
SM_DRAMRST#
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
F6
AL1
AM1
AN1
AN15
AP15
SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2
PM_EXTTS#0
PM_EXTTS#1_R
SM_DRAMRST# <10>
PECI
1
R28
2
100K_0402_5%
R32
R34
R35
2009/08/14 #425302
CP_S3PowerReduction
WhitePaper_Rev0.9
+1.05VS_VTT
<45> H_PROCHOT#
H_PROCHOT#
AN26
PROCHOT#
DDR3
MISC
PM_EXT_TS#[0]
PM_EXT_TS#[1]
1
1
1
2
10K_0402_5%
2
10K_0402_5%
2
0_0402_5%
XDP_PRDY#
XDP_TMS
XDP_TDI_R
XDP_PREQ#
XDP_TCLK
R27
R29
R30
R31
R33
1
1
1
1
1
@
@
@
@
@
2
2
2
2
2
51_0402_5%
51_0402_5%
51_0402_5%
51_0402_5%
51_0402_5%
PM_EXTTS#0_1 <10,11>
<18> H_THERMTRIP#
R36
1
0_0402_5%
2
H_THERMTRIP#_R
AK15
THERMTRIP#
XDP_TRST#
R37
PRDY#
PREQ#
H_CPURST#
R42
1
0_0402_5%
R44
1
0_0402_5%
C
AT28
AP27
AN28
AP28
AT27
AT29
AR27
AR29
AP29
AN25
AJ22
AK22
AK24
AJ24
AJ25
AH22
AK23
AH23
XDP_PRDY#
XDP_PREQ#
XDP_TCLK
XDP_TMS
XDP_TRST#
XDP_TDI_R
XDP_TDO_R
XDP_TDI_M
XDP_TDO_M
XDP_DBR#_R
R46
1
2
51_0402_5%
AP26
AL15
AN14
AN27
AK13
AM15
AM26
AL14
RESET_OBS#
PM_SYNC
VCCPWRGOOD_1
VCCPWRGOOD_0
SM_DRAMPWROK
VTTPWRGOOD
TAPPWRGOOD
RSTIN#
JTAG & BPM
TCK
TMS
TRST#
TDI
TDO
TDI_M
TDO_M
DBR#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
SM_RCOMP_0 R38
SM_RCOMP_1 R39
SM_RCOMP_2 R40
1
2
100_0402_1%
1
2
24.9_0402_1%
<BOM Structure>
1
2
130_0402_1%
XDP_TDI_R
XDP_TDO_M
R41
R43
PWR MANAGEMENT
PWR MANAGEMENT
<15> H_PM_SYNC
2
2
2
2
H_PM_SYNC_R
H_CPUPWRGD_1
H_CPUPWRGD_0
1
1
@
2
0_0402_5%
2
0_0402_5%
XDP_TDI
XDP_TDO
1
1
2
0_0402_5% XDP_DBRESET#
R45
0_0402_5%
XDP_DBRESET# <15,21>
XDP_TDI_M
XDP_TDO_R
<18> H_CPUPWRGD
<15> PM_DRAM_PWRGD
R47
1
0_0402_5%
R50
1
0_0402_5%
2
C
PM_DRAM_PWRGD_R
H_VTTPWRGD
1
@
R52
H_PWRGD_XDP
R55
1
0_0402_5%
2
H_VTTPWRGD_R
0_0402_5%
2
H_PWRGD_XDP_R
PLT_RST#_R
XDP_OBS0
XDP_OBS1
XDP_OBS2
XDP_OBS3
XDP_OBS4
XDP_OBS5
XDP_OBS6
XDP_OBS7
R48
R49
1
@
1
2
2
0_0402_5%
0_0402_5%
JTAG MAPPING
Scan Chain
(Default)
CPU Only
STUFF -> R653, R657, R662
NO STUFF -> R655, R660
STUFF -> R653, R655
NO STUFF -> R657, R660, R662
STUFF -> R660, R662
NO STUFF -> R653, R655, R657
<17,21,27,30> PLT_RST#
R56
1
1.5K_0402_1%
2
1
2009/2/4
#414044 DG
Update Rev1.11
+1.05VS_VTT
R57
750_0402_1%
IC,AUB_CFD_rPGA,R1P0
CONN@
2009/2/4
Delete dampling resistor for
power noise and Layout space
issue
GMCH Only
2
R58
R59
R60
B
2
2
2
1
49.9_0402_1%
1
68_0402_5%
@
1
68_0402_5%
H_CATERR#
H_PROCHOT#
H_CPURST#
JP5
XDP Connector
GND1
OBSFN_C0
OBSFN_C1
GND3
OBSDATA_C0
OBSDATA_C1
GND5
OBSDATA_C2
OBSDATA_C3
GND7
OBSFN_D0
OBSFN_D1
GND9
OBSDATA_D0
OBSDATA_D1
GND11
OBSDATA_D2
OBSDATA_D3
GND13
ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
GND15
TD0
TRST#
TDI
TMS
GND17
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
B
+3VALW
2009/8/14
change back to 2K
R61
2K_0402_1%
1
2
XDP_PREQ#
XDP_PRDY#
XDP_OBS0
XDP_OBS1
U1
<43> H_VTTPWRGD
H_VTTPWRGD
2
B
A
G
1
1
Y
3
4
H_VTTPWRGD_R
R62
1K_0402_1%
XDP_OBS2
XDP_OBS3
NC7SZ08P5X_NL_SC70-5
U1 / U2
change to SA00000OH00
#425302
CP_S3PowerReduction
WhitePaper_Rev0.7
+1.5V_1
+3VALW
XDP_OBS4
XDP_OBS5
R65
1K_0402_5%
H_CPUPWRGD
1
1
<15,21,30> PBTN_OUT#
R66
+1.05VS_VTT
C65
1
0.1U_0402_16V4Z
@
XDP_OBS6
XDP_OBS7
Need to check Voltage Level
5
U2
4
1
1
B
A
2
1
P
H_VTTPWRGD
Y
G
3
2
H_PWRGOOD_R
2
PBTN_OUT#_XDP
0_0402_5%
H_PWRGD_XDP
NC7SZ08P5X_NL_SC70-5
R68
@
1.1K_0402_1%
R69
1.5K_0402_1%
2
<21> SMB_DATA_S3
<21> SMB_CLK_S3
XDP_TCLK
2
A
2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
GND0
OBSFN_A0
OBSFN_A1
GND2
OBSDATA_A0
OBSDATA_A1
GND4
OBSDATA_A2
OBSDATA_A3
GND6
OBSFN_B0
OBSFN_B1
GND8
OBSDATA_B0
OBSDATA_B1
GND10
OBSDATA_B2
OBSDATA_B3
GND12
PWRGOOD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
GND14
SDA
SCL
TCK1
TCK0
GND16
CONN@
P
5
H_RESET#_R
R63
1K_0402_5%
1
2
H_CPURST#
1
2
PLT_RST#
R64
@
0_0402_5%
2
CLK_CPU_XDP
CLK_CPU_XDP#
H_RESET#_R
XDP_DBRESET#
XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS
+1.05VS_VTT
1
R67
1
R70
2
1K_0402_5%
2
51_0402_5%
+3VS
+1.05VS_VTT
A
PM_DRAM_PWRGD_R
SAMTE_BSH-030-01-L-D-A
1
1
R72
750_0402_1%
R71
@
3.01K_0402_1%
Security Classification
Issued Date
2009/08/01
Compal Secret Data
Deciphered Date
2010/08/01
Title
Compal Electronics, Inc.
SCHEMATICS,MB A5892
Document Number
Rev
C
Sheet
1
2009/04/23
Intel CRB 1.55 Update
Change R292 to 1.1K_1%, R302 to 3.01K_1%
4
2
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
401826
Tuesday, June 22, 2010
5
of
49
Date:
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