Acer Aspire 5330_5730_Wistron_Cathedral_Peak_Rev-1.pdf

(1984 KB) Pobierz
5
4
3
2
1
Cathedral Peak Block Diagram
D
Project code: 91.4J501.001
PCB P/N
: 48.4J501.001
REVISION
: 07261 - 1
SYSTEM DC/DC
PCB STACKUP
TPS51125
INPUTS
43
OUTPUTS
5V_S5
DCBATOUT
3D3V_S5
D
CLK GEN.
ICS 9LPRS365BKLFT (71.09365.A03)
RTM 875N-606-LFT (71.00875.003)
3
Mobile CPU
Penryn 479
4, 5
THERMAL EMC2102
21
TOP
VCC
DDR2 DIMM1
667/800 MHz
12
HOST BUS
667/800MHz
667/800/1067MHz@1.05V
CRT
S
S
15
GND
BOTTOM
Cantiga
AGTL+ CPU I/F
DDR Memory I/F
INTEGRATED GRAHPICS
LVDS, CRT I/F
LCD
SYSTEM DC/DC
TPS51124
INPUTS
DCBATOUT
1D8V_S3
1D05V_S0
14
45
OUTPUTS
DDR2 DIMM2
667/800 MHz
13
C
667/800MHz
6,7,8,9,10,11
INT.MIC
29
X4 DMI
400MHz
RT9026
1D8V_S3
44
DDR_VREF_S0
DDR_VREF_S3
C
C-Link0
Line In
29
Codec
ALC268
28
ICH9M
AZALIA
6 PCIe ports
PCI/PCI BRIDGE
ACPI 2.0
4 SATA
12 USB 2.0/1.1 ports
ETHERNET (10/100/1000MbE)
High Definition Audio
LPC I/F
Serial Peripheral I/F
Matrix Storage Technology(DO)
Active Managemnet Technology(DO)
RT9018A
44
1D5V_S0
PCIex1
Giga LAN
88E8071
25
LAN
TXFM
26
RJ45
26
1D8V_S3
CFXCORE DC/DC
ISL6263
INPUTS
DCBATOUT
MIC In
29
PCIex1
PCIex1
New card
27
PWR SW
G577BR91U
27
35,36
OUTPUTS
VGFXCORE
0.7~1.25V
Mini Card
Kedron a/b/g/n
29
B
OP AMP
APA2057
29
27
CPU DC/DC
LPC BUS
BIOS
Winbond
W25X80
8M Bits
INT.SPKR
29
ISL6266A
INPUTS
OUTPUTS
42
B
KBC
ENE3310
LPC
31
DCBATOUT
VCC_CORE_S0
0.35~1.5V
Line Out
(NO SPDIF)
RJ11
MODEM
MDC Card
23
17,18,19,20
30
DEBUG
31
CONN.
BQ24750
INPUTS
USB
Blue Tooth
23
(USB)
Camera
(USB)
14
Launch
Buttom
16
CHARGER
47
OUTPUTS
BT+
DCBATOUT
Touch
Pad
30
INT.
KB
30
MS/MS Pro/xD
/MMC/SD
5 in 1
SATA
HDD SATA
22
A
USB
2 Port
USB
23
CardReader
Realtek
27
RTS5158E
DCBATOUT
27
A
ODD SATA
22
Wistron Corporation
SATA
Daughter Board
LED Board
07950
16
Daughter Board
USB Board
2 Port + e-Key
07951
23
2
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
BLOCK DIAGRAM
Size
A3
Document Number
Rev
Cathedral Peak
Sheet
1
-1
of
42
Date: Monday, May 05, 2008
5
4
3
1
A
B
page 92
C
ICH9M Functional Strap Definitions
Rev.1.5
ICH9 EDS 642879
Signal
HDA_SDOUT
Usage/When Sampled
XOR Chain Entrance/
PCIE Port Config1 bit1,
Rising Edge of PWROK
Comment
ICH9M Integrated Pull-up
and Pull-down Resistors
ICH9 EDS 642879
Cantiga chipset and ICH9M I/O controller
Hub strapping configuration
Rev.1.5
Pin Name
CFG[2:0]
D
E
Montevina Platform Design guide 22339
page 218
Strap Description
FSB Frequency
Select
Configuration
000 = FSB1067
011 = FSB667
010 = FSB800
others = Reserved
0.5
Allows entrance to XOR Chain testing when TP3
pulled low.When TP3 not pulled low at rising edge
of PWROK,sets bit1 of RPC.PC(Config Registers:
offset 224h). This signal has weak internal pull-down
This signal has a weak internal pull-down.
Sets bit0 of RPC.PC(Config Registers:Offset 224h)
This signal has a weak internal pull-up.
Sets bit2 of RPC.PC2(Config Registers:Offset 0224h)
This signal should not be pulled high.
ESI compatible mode is for server platforms only.
This signal should not be pulled low for desttop
and mobile.
Sampled low:Top-Block Swap mode(inverts A16 for
all cycles targeting FWH BIOS space).
Note: Software will not be able to clear the
Top-Swap bit until the system is rebooted
without GNT3# being pulled down.
Controllable via Boot BIOS Destination bit
(Config Registers:Offset 3410h:bit 11:10).
GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC.
Sample low: the Integrated TPM will be disabled.
Sample high: the MCH TPM enable strap is sampled
low and the TPM Disable bit is clear, the
Integrated TPM will be enable.
SIGNAL
CL_CLK[1:0]
CL_DATA[1:0]
CL_RST0#
DPRSLPVR/GPIO16
ENERGY_DETECT
HDA_BIT_CLK
HDA_DOCK_EN#/GPIO33
HDA_RST#
HDA_SDIN[3:0]
HDA_SDOUT
HDA_SYNC
GLAN_DOCK#
GPIO[20]
GPIO[49]
LDA[3:0]#/FHW[3:0]#
LAN_RXD[2:0]
LDRQ[0]
LDRQ[1]/GPIO23
PME#
PWRBTN#
SATALED#
SPI_CS1#/GPIO58/CLGPIO6
GNT[3:0]#/GPIO[55,53,51]
Resistor Type/Value
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-DOWN 20K
PULL-UP 20K
PULL-DOWN 20K
PULL-UP 20K
PULL-DOWN 20K
PULL-DOWN 20K
PULL-DOWN 20K
PULL-DOWN 20K
4
HDA_SYNC
GNT2#/
GPIO53
GPIO20
GNT1#/
GPIO51
PCIE config1 bit0,
Rising Edge of PWROK.
PCIE config2 bit2,
Rising Edge of PWROK.
Reserved
ESI Strap (Server Only)
Rising Edge of PWROK
CFG[4:3]
CFG8
CFG[15:14]
CFG[18:17]
CFG5
CFG6
Reserved
4
DMI x2 Select
iTPM Host
Interface
Intel Management
engine Crypto strap
0 = DMI x2
1 = DMI x4
(Default)
0= The iTPM Host Interface is enabled(Note2)
1=The iTPM Host Interface is disalbed(default)
0 = Transport Layer Security (TLS) cipher
suite with no confidentiality
1 = TLS cipher suite with
confidentiality (default)
0 = Reverse Lanes,15->0,14->1 ect..
1= Normal operation(Default):Lane
Numbered in order
0 = Enable (Note 3)
1= Disabled (default)
00
10
01
11
=
=
=
=
Reserve
XOR mode Enabled
ALLZ mode Enabled (Note 3)
Disabled (default)
GNT3#/
GPIO55
Top-Block
Swap Override.
Rising Edge of PWROK.
CFG7
The pull-up or pull-down active when configured for native
CFG9
GLAN_DOCK# functionality and determined by LAN controller
PCIE Graphics Lane
GNT0#:
SPI_CS1#/
GPIO58
Boot BIOS Destination
Selection 0:1.
Rising Edge of PWROK.
Integrated TPM Enable,
Rising Edge of CLPWROK
PULL-UP 20K
PULL-DOWN 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 15K
PULL-UP 20K
PULL-DOWN 20K
PULL-UP 20K
PULL-DOWN 20K
PULL-UP 20K
PULL-UP 20K
PULL-DOWN 15K
L_DDC_DATA
Local Flat Panel
(LFP) Present
SDVO_CTRLDATA
SDVO Present
CFG20
CFG19
DMI Lane Reversal
CFG16
FSB Dynamic ODT
CFG10
CFG[13:12]
PCIE Loopback enable
XOR/ALL
SPI_MOSI
3
GPIO49
DMI Termination Voltage, The signal is required to be low for desktop
Rising Edge of PWROK.
applications and required to be high for
mobile applications.
0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled (Default)
0 = Normal operation(Default):
Lane Numbered in Order
3
SATALED#
SPKR
PCI Express Lane
Reversal. Rising Edge
of PWROK.
No Reboot.
Rising Edge of PWROK.
Signal has weak internal pull-up. Sets bit 27
of MPC.LR(Device 28:Function 0:Offset D8)
If sampled high, the system is strapped to the
"No Reboot" mode(ICH9 will disable the TCO Timer
system reboot feature). The status is readable
via the NO REBOOT bit.
This signal should not be pull low unless using
XOR Chain testing.
Sampled low:the Flash Descriptor Security will be
overridden. If high,the security measures will be
in effect.This should only be enabled in manufacturing
environments using an external pull-up resister.
1 = Reverse Lanes
DMI x4 mode[MCH -> ICH]:(3->0,2->1,1->2and0->3)
DMI x2 mode[MCH -> ICH]:(3->0,2->1)
Digital Display Port
(SDVO/DP/iHDMI)
Concurrent with PCIe
0 = Only Digital Display Port
or PCIE is operational (Default)
1 =Digital display Port and PCIe are
operting simulataneously via the PEG port
0 =No SDVO Card Present (Default)
1 = SDVO Card Present
0 = LFP Disabled (Default)
1= LFP Card Present; PCIE disabled
SPI_MOSI
SPI_MISO
SPKR
TACH_[3:0]
TP[3]
USB[11:0][P,N]
TP3
XOR Chain Entrance.
Rising Edge of PWROK.
Flash Descriptor
Security Override Strap
Rising Edge of PWROK
GPIO33/
HDA_DOCK
_EN#
2
NOTE:
1. All strap signals are sampled with respect to the leading edge of
the (G)MCH Power OK (PWROK) signal.
2. iTPM can be disabled by a 'Soft-Strap' option in the
Flash-decriptor section of the Firmware. This 'Soft-Strap' is
activated only after enabling iTPM via CFG6.
Only one of the CFG10/CFG/12/CFG13 straps can be enabled at any time.
2
SMBus
EMC2102
Thermal
USB Table
USB
KBC
BAT_SCL
PCIE Routing
LANE1
LANE2
LANE3
LANE4
LANE5
LANE6
LAN MARVELL 88E8071
MiniCard WLAN
NC
NC
NewCard
NC
Pair
0
1
2
3
4
5
6
7
8
9
10
11
Device
USB1
USB4
USB2
NC
USB3
Bluetooth
NC
MINIC1
WEBCAM
NEW1
Card Reader
NC
SMBC_ICH
BATTERY
1
ICH9M
1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
9LPRS365BKLFT
DDR
Size
A3
Reference
Document Number
Rev
Cathedral Peak
Sheet
2
of
42
-1
Date: Monday, May 05, 2008
A
B
C
D
E
3D3V_S0
3D3V_S0
3D3V_S0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
C190
SC4D7U6D3V3KX-GP
C183
SC1U16V3ZY-GP
EC58
SCD1U16V2ZY-2GP
C463
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C235
SC4D7U10V5ZY-3GP
C459
SCD1U16V2ZY-2GP
C465
SCD1U16V2ZY-2GP
C231
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C246
SCD1U16V2ZY-2GP
C195
SC4D7U10V5ZY-3GP
C214
SCD1U16V2ZY-2GP
C453
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C198
SCD1U16V2ZY-2GP
1
1
R146
2
0R0603-PAD
3D3V_48MPWR_S0
3D3V_CLKPLL_S0
1
R197
2
0R0603-PAD
C462
SCD1U16V2ZY-2GP
3D3V_CLKGEN_S0
1
R157
2
0R0603-PAD
C234
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C184
SCD1U16V2ZY-2GP
DY
2
DY
2
DY
DY
2
DY
2
DY
DY
2
2
2
2
2
2
2
2
2
2
2
4
2
4
3D3V_CLKGEN_S0
PCLK_ICH
CLK_ICH14
1
2
DY
2
4
16
9
46
62
23
VDDREF
VDD48
VDDPCI
VDDSRC
VDDCPU
VDDPLL3
VDD96_IO
VDDPLL3_IO
VDDSRC_IO
VDDSRC_IO
VDDSRC_IO
VDDCPU_IO
19
27
43
52
33
56
CLK_CPU_BCLK_1
CLK_CPU_BCLK_1#
CLK_MCH_BCLK_1
CLK_MCH_BCLK_1#
CLK_PCIE_LAN_R
CLK_PCIE_LAN#_R
CLK_PCIE_NEW_R
CLK_PCIE_NEW#_R
CLK_PCIE_ICH_1
CLK_PCIE_ICH_1#
R160
1
R166
1
R167
1
R169
1
R173
1
R176
1
R182
1
R181
1
R195
1
R194
1
EC57
SC5P50V2CN-2GP
1
1
EC55
SC5P50V2CN-2GP
CLK48_ICH
EC137
SC5P50V2CN-2GP
3D3V_48MPWR_S0
3D3V_CLKPLL_S0
DY
U19
DY
CL=20pF±0.2pF
C177
SC27P50V2JN-2-GP
GEN_XTAL_IN
1
2
R154
2
2
DY
1
10MR2J-L-GP
1
0R0402-PAD
GEN_XTAL_OUT
RN51
CPUT0
CPUC0
CPUT1_F
CPUC1_F
CPUT2_ITP/SRCT8
CPUC2_ITP/SRCC8
61
60
58
57
54
53
51
50
48
47
41
42
40
39
37
38
34
35
31
32
28
29
24
25
20
21
2
0R0402-PAD
2
0R0402-PAD
2
0R0402-PAD
2
0R0402-PAD
2
0R0402-PAD
2
0R0402-PAD
2
0R0402-PAD
2
0R0402-PAD
2
0R0402-PAD
2
0R0402-PAD
CLK_CPU_BCLK 4
CLK_CPU_BCLK# 4
CLK_MCH_BCLK 6
CLK_MCH_BCLK# 6
CLK_PCIE_LAN 25
CLK_PCIE_LAN# 25
CLK_PCIE_NEW 27
CLK_PCIE_NEW# 27
CLK_PCIE_ICH 18
CLK_PCIE_ICH# 18
CPU
NB
LAN
New Card
SB DMI
3
X3
X-14D31818M-44GP
2
R153
24
18
4,7
3
2
4
SRN33J-5-GP-U
3
82.30005.951
2
1
2
GEN_XTAL_OUT_R
SA
CLK48
17
X1
X2
1
CLK48_5158E
CLK48_ICH
CPU_SEL0
1
2
2
R156
1
USB_48MHZ/FSLA
SRCT7/CR#_F
SRCC7/CR#_E
PCI_STOP#
CPU_STOP#
SRCT6
SRCC6
SRCT10
SRCC10
SRCT11/CR#_H
SRCC11/CR#_G
SRCT9
SRCC9
PCI0/CR#_A
PCI1/CR#_B
PCI2/TME
PCI3
PCI4/27_SELECT
PCI_F5/ITP_EN
SRCT4
SRCC4
SRCT3/CR#_C
SRCC3/CR#_D
SRCT2/SATAT
SRCC2/SATAC
FSLB/TEST_MODE
REF0/FSLC/TEST_SEL
NC#55
GND
GNDSRC
GNDSRC
GNDSRC
GNDCPU
GND
GND48
GNDPCI
GNDREF
27MHZ_NONSS/SRCT1/SE1
27MHZ_SS/SRCC1/SE2
SRCT0/DOTT_96
SRCC0/DOTC_96
-1
3
C176
SC27P50V2JN-2-GP
2K2R2J-2-GP
18 PM_STPPCI#
18 PM_STPCPU#
3D3V_S0
0505 Sawp nets for
0505 Sawp nets for
CPU_SEL2
PCLKCLK2 and CPU_SEL2_R
3D3V_S0 and CPU_SEL2
3D3V_S0
4,7
45
44
12,13,20 SMBC_ICH
12,13,20 SMBD_ICH
7
6
63
SCLK
SDATA
CK_PWRGD/PD#
SA
RN59
SRN10KJ-6-GP
TPAD30 TP158
7
2
R155
DY
18 CLK_PWRGD
1
10KR2J-3-GP
R150
1
DY
2
475R2F-L1-GP
PCLKCLK0
PCLKCLK1
PCLKCLK2
PCLKCLK3
PCLKCLK4
PCLKCLK5
8
7
6
5
CLK_MCH_OE#
CPU_SEL2_R
PCLKCLK2
PCLKCLK4
PCLKCLK5
30
18
PCLK_KBC
PCLK_ICH
RN17
1
2
4
3
8
10
11
12
13
14
1
2
3
4
CLK_PCIE_MINI_1
CLK_PCIE_MINI_1#
CLK_MCH_3GPLL_1
CLK_MCH_3GPLL_1#
CLK_PCIE_SATA_1
CLK_PCIE_SATA_1#
DREFSSCLK_1
DREFSSCLK#_1
DREFCLK_1
DREFCLK#_1
R192
1
R193
1
R180
1
R184
1
R174
1
R177
1
R168
1
R171
1
R158
1
R161
1
2
0R0402-PAD
2
0R0402-PAD
2
0R0402-PAD
2
0R0402-PAD
2
0R0402-PAD
2
0R0402-PAD
2
0R0402-PAD
2
0R0402-PAD
2
0R0402-PAD
2
0R0402-PAD
CLK_PCIE_MINI1 27
CLK_PCIE_MINI1# 27
CLK_MCH_3GPLL 7
CLK_MCH_3GPLL# 7
CLK_PCIE_SATA 17
CLK_PCIE_SATA# 17
DREFSSCLK 7
DREFSSCLK# 7
DREFCLK 7
DREFCLK# 7
MINI1
NB CLK
SB SATA
NB CLK
NB CLK
(96 MHz)
SRN33J-5-GP-U
PCLK_KBC
4,7
CPU_SEL1
64
CPU_SEL2_R
5
1
-1
EC56
SC5P50V2CN-2GP
18
31
CLK_ICH14
PCLK_FWH
1
2
4
3
PCLKCLK3
55
2
ICS9LPRS365BKLFT setting table
PIN NAME
DESCRIPTION
PCI0/CR#_A
Byte 5, bit 7
0 = PCI0 enabled (default)
1= CR#_A enabled. Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair
Byte 5, bit 6
0 = CR#_A controls SRC0 pair (default),
1= CR#_A controls SRC2 pair
Byte 5, bit 5
0 = PCI1 enabled (default)
1= CR#_B enabled. Byte 5, bit 6 controls whether CR#_B controls SRC1 or SRC4 pair
Byte 5, bit 4
0 = CR#_B controls SRC1 pair (default)
1= CR#_B controls SRC4 pair
0 = Overclocking of CPU and SRC Allowed
1 = Overclocking of CPU and SRC NOT allowed
3.3V PCI clock output
18
15
1
22
30
36
49
59
26
71.09365.A03
65
ICS9LPRS365BKLFT-GP
GND
2
DY
RN70
SRN33J-5-GP-U
2
2nd:
71.00875.C03
RTM875N-606-LFT QFN 64P
SEL2 SEL1 SEL0
FSC FSB FSA
PIN NAME
SRCC3/CR#_D
SRCC7/CR#_E
DESCRIPTION
Byte 5, bit 1
0 = SRC3 enabled (default)
1= CR#_D enabled. Byte 5, bit 0 controls whether CR#_D controls SRC1 or SRC4 pair
Byte 5, bit 0
0 = CR#_D controls SRC1 pair (default)
1= CR#_D controls SRC4 pair
Byte 6, bit 7
0 = SRC7# enabled (default)
1= CR#_F controls SRC6
Byte 6, bit 6
0 = SRC7 enabled (default)
1= CR#_F controls SRC8
Byte 6, bit 5
0 = SRC11# enabled (default)
1= CR#_G controls SRC9
Title
Byte 6, bit 4
0 = SRC11 enabled (default)
1= CR#_H controls SRC10
CPU
100M
133M
166M
200M
266M
FSB
X
533M
667M
800M
1066M
1
PCI1/CR#_B
PCI2/TME
PCI3
1
1
0
0
0
0
0
0
1
1
0
1
1
1
0
0
PCI4/27M_SEL
PCI_F5/ITP_EN
SRCT3/CR#_C
0 = Pin24 as SRC-1, Pin25 as SRC-1#, Pin20 as DOT96, Pin21 as DOT96#
1 = Pin24 as 27MHz, Pin25 as 27MHz_SS, Pin20 as SRC-0, Pin21 as SRC-0#
0 =SRC8/SRC8#
1 = ITP/ITP#
Byte 5, bit 3
0 = SRC3 enabled (default)
1= CR#_C enabled. Byte 5, bit 2 controls whether CR#_C controls SRC0 or SRC2 pair
Byte 5, bit 2
0 = CR#_C controls SRC0 pair (default),
1= CR#_C controls SRC2 pair
SRCT7/CR#_F
SRCC11/CR#_G
SRCT11/CR#_H
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Clock Generator
Document Number
Rev
Size
Cathedral Peak
Date: Friday, May 16, 2008
A
B
C
D
-1
of
42
Sheet
E
3
A
B
C
D
E
6
H_A#[35..3]
H_A#[35..3]
H_DINV#[3..0]
U33A
1 OF 4
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
TP57 TPAD30
H_DSTBN#[3..0]
6
6
6
1D05V_S0
H_DSTBP#[3..0]
H_D#[63..0]
H_DINV#[3..0]
H_DSTBN#[3..0]
H_DSTBP#[3..0]
H_D#[63..0]
6
6
6
6
4
4
6
6
H_ADSTB#0
H_REQ#[4..0]
J4
L5
L4
K5
M3
N2
J1
N3
P5
P2
L2
P4
P1
R1
M1
A3#
A4#
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
ADSTB0#
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#
A32#
A33#
A34#
A35#
ADSTB1#
A20M#
FERR#
IGNNE#
STPCLK#
LINT0
LINT1
SMI#
RSVD#M4
RSVD#N5
RSVD#T2
RSVD#V3
RSVD#B2
RSVD#C3
RSVD#D2
RSVD#D22
RSVD#D3
RSVD#F6
KEY_NC
ADS#
BNR#
BPRI#
H1
E2
G5
H5
F21
E1
F1
D20
B3
H4
C1
F3
F4
G3
G2
G6
E4
AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20
XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
XDP_DBRESET#
H_RS#0
H_RS#1
H_RS#2
H_ADS#
H_BNR#
H_BPRI#
ADDR GROUP 0
CONTROL
DEFER#
DRDY#
DBSY#
BR0#
IERR#
INIT#
LOCK#
RESET#
RS0#
RS1#
RS2#
TRDY#
HIT#
HITM#
H_DEFER# 6
H_DRDY# 6
H_DBSY# 6
H_BREQ#0 6
H_IERR#
H_INIT#
17
1
R125
56R2J-4-GP
Place testpoint on
H_IERR# with a GND
0.1" away
2
TP95 TPAD30
3
Side Band
Non GTL
6
17
17
17
17
17
17
17
H_ADSTB#1
H_A20M#
H_FERR#
H_IGNNE#
H_STPCLK#
H_INTR
H_NMI
H_SMI#
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TP52
TP49
TP48
TP47
TP89
TP92
TP87
TP90
TP88
TP72
TP93
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
Y2
U5
R3
W6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
U2
V4
W3
AA4
AB2
AA3
V1
A6
A5
C4
D5
C6
B4
A3
H_HIT#
H_HITM#
TP27
TP25
TP28
TP41
TP30
TP37
TP29
TP39
TP40
TP44
TP34
TP91
6
6
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
TPAD30
H_THERMDA
XDP/ITP SIGNALS
BPM0#
BPM1#
BPM2#
BPM3#
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
DBR#
DY
H_THERMDC
1D05V_S0
6
6
6
H_DSTBN#0
H_DSTBP#0
H_DINV#0
2
C136
SC2200P50V2KX-2GP
DATA GRP2
H_REQ#0
K3
H_REQ#1
H2
H_REQ#2
K2
H_REQ#3
J3
H_REQ#4
L1
H_LOCK# 6
H_CPURST# 6,41
H_RS#[2..0]
U33B
2 OF 4
6
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_TRDY# 6
R123
68R2-GP
E22
F24
E26
G22
F23
G25
E25
E23
K24
G24
J24
J23
H22
F26
K22
H23
J26
H26
H25
D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
D13#
D14#
D15#
DSTBN0#
DSTBP0#
DINV0#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
DSTBN1#
DSTBP1#
DINV1#
GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
BSEL0
BSEL1
BSEL2
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
DSTBN2#
DSTBP2#
DINV2#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
DSTBN3#
DSTBP3#
DINV3#
COMP0
COMP1
COMP2
COMP3
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PSI#
Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22
AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20
R26
U26
AA1
Y1
E5
B5
D24
D6
D7
AE6
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2 6
H_DSTBP#2 6
H_DINV#2 6
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3 6
H_DSTBP#3 6
H_DINV#3 6
COMP0
COMP1
COMP2
COMP3
R105
R104
R98
R99
DATA GRP0
1
2
THERMTRIP#
C7
PM_THRMTRIP-A# 7,17,32
HCLK
BCLK0
BCLK1
A22
A21
CLK_CPU_BCLK 3
CLK_CPU_BCLK# 3
PM_THRMTRIP#
should connect to
ICH9 and MCH
without T-ing
( No stub)
Layout Note:
"CPU_GTLREF0"
0.5" max length.
1D05V_S0
2
RSVD_CPU_1
RSVD_CPU_2
RSVD_CPU_3
RSVD_CPU_4
RSVD_CPU_5
RSVD_CPU_6
RSVD_CPU_7
RSVD_CPU_8
RSVD_CPU_9
RSVD_CPU_10
RSVD_CPU_11
M4
N5
T2
V3
B2
C3
D2
D22
D3
F6
B1
2
RESERVED
R263
1KR2F-3-GP
6
6
6
H_DSTBN#1
H_DSTBP#1
H_DINV#1
1
CPU_GTLREF0
DATA GRP3
1
1
BGA479-SKT6-GPU6
2
2
ADDR GROUP 1
3
1
THERMAL
PROCHOT#
THRMDA
THRMDC
D21
A24
B25
CPU_PROCHOT#
H_THERMDA 21
H_THERMDC 21
1
R124
DY
2
CPU_PROCHOT#_R
34
0R2J-2-GP
H_D#16
N22
H_D#17
K25
H_D#18
P26
H_D#19
R23
H_D#20
L23
H_D#21
M24
H_D#22
L22
H_D#23
M23
H_D#24
P25
H_D#25
P23
H_D#26
P22
H_D#27
T24
H_D#28
R24
H_D#29
L25
H_D#30
T25
H_D#31
N25
L26
M26
N24
DATA GRP1
ICH
1D05V_S0
R266
2KR2F-3-GP
DY
C352
SC1KP50V2KX-1GP
TPAD30 TP86
TPAD30
TPAD30
TP21
TP150
AD26
TEST1
C23
TEST2
D25
RSVD_CPU_12
C24
TEST4
AF26
RSVD_CPU_13
AF1
RSVD_CPU_14
A26
B22
B23
C21
MISC
1
1
1
1
2
2
2
2
27D4R2F-L1-GP
54D9R2F-L1-GP
27D4R2F-L1-GP
54D9R2F-L1-GP
2
62.10079.001
2nd: 62.10053.401
3,7
3,7
3,7
CPU_SEL0
CPU_SEL1
CPU_SEL2
H_DPRSTP# 7,17,34
H_DPSLP# 17
H_DPWR# 6
H_PWRGD 17,32,41
H_CPUSLP# 6
PSI#
34
BGA479-SKT6-GPU6
62.10079.001
Follow Demo Circuit
XDP_TMS
XDP_TDI
XDP_BPM#5
R102
1
R101
1
R97
2
54D9R2F-L1-GP
2
54D9R2F-L1-GP
2
54D9R2F-L1-GP
1
R118
1
R295
2
C351
1
DY
DY
2
2
TEST1
1KR2J-1-GP
TEST2
1KR2J-1-GP
Net "TEST4" as short as possible,
make sure "TEST4" routing is
reference to GND and away other
noisy signals
Layout Note:
Comp0, 2 connect with Zo=27.4 ohm, make
trace length shorter than 0.5" .
Comp1, 3 connect with Zo=55 ohm, make
trace length shorter than 0.5" .
H_CPURST#
XDP_TCK
1
R116
1
R94
R96
DY
2
51R2F-2-GP
2
54D9R2F-L1-GP
2
54D9R2F-L1-GP
1
1
TEST4
1
SCD1U10V2KX-4GP
XDP_TRST#
DY
3D3V_S0
1
All place within 2" to CPU
XDP_DBRESET#
R121
1
DY
2
1KR2J-1-GP
1D05V_S0
Title
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
XDP_TDO
R100
1
DY
2
54D9R2F-L1-GP
Size
Document Number
CPU (1 of 2)
Rev
Cathedral Peak
Date: Friday, May 16, 2008
A
B
C
D
-1
4
of
42
Sheet
E
A
B
C
D
E
VCC_CORE
VCC_CORE
4
VCC_CORE
VCC_CORE
U33D
4 OF 4
VCC_CORE
SB
A4
A8
A11
A14
A16
A19
A23
AF2
B6
B8
B11
B13
B16
B19
B21
B24
C5
C8
C11
C14
C16
C19
C2
C22
C25
D1
D4
D8
D11
D13
D16
D19
D23
D26
E3
E6
E8
E11
E14
E16
E19
E21
E24
F5
F8
F11
F13
F16
F19
F2
F22
F25
G4
G1
G23
G26
H3
H6
H21
H24
J2
J5
J22
J25
K1
K4
K23
K26
L3
L6
L21
L24
M2
M5
M22
M25
N1
N4
N23
N26
P3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25
4
1
1
1
1
1
1
1
1
C86
SCD1U10V2KX-4GP
C120
SCD1U10V2KX-4GP
C122
SCD1U10V2KX-4GP
C88
SCD1U10V2KX-4GP
C90
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C124
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C130
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
C89
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1
4
TC9
ST900U2D5VM-1-GP
U33C
3 OF 4
3
2
A7
A9
A10
A12
A13
A15
A17
A18
A20
B7
B9
B10
B12
B14
B15
B17
B18
B20
C9
C10
C12
C13
C15
C17
C18
D9
D10
D12
D14
D15
D17
D18
E7
E9
E10
E12
E13
E15
E17
E18
E20
F7
F9
F10
F12
F14
F15
F17
F18
F20
AA7
AA9
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AB9
AC10
AB10
AB12
AB14
AB15
AB17
AB18
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCA
VCCA
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VCCSENSE
VSSSENSE
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
G5
DY
DY
2
DY
2
DY
2
2
2
2
2
DY
DY
DY
DY
2
NEC
77.E9071.011
TP22
TPAD30
VCC_CORE
1
1
1
1
1
1
1
1
1
1
1
1
1
2
3
C123
SC10U6D3V5MX-3GP
C102
SC10U6D3V5MX-3GP
C135
SC10U6D3V5MX-3GP
C93
SC10U6D3V5MX-3GP
C380
SC10U6D3V5MX-3GP
C375
SC10U6D3V5MX-3GP
C381
SC10U6D3V5MX-3GP
C374
SC10U6D3V5MX-3GP
C70
SC10U6D3V5MX-3GP
C94
SC10U6D3V5MX-3GP
C106
SC10U6D3V5MX-3GP
C71
SC10U6D3V5MX-3GP
C103
SC10U6D3V5MX-3GP
1
2
C105
SC10U6D3V5MX-3GP
DY
2
DY
2
DY
2
DY
2
DY
2
DY
2
DY
2
DY
2
2
2
2
2
CAP
CAP
CAP
CAP
CAP
CAP
2
3
1D05V_S0
VCCP_1D05
G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
B26
C26
AD6
AF5
AE5
AF4
AE3
AF3
AE2
AF7
AE7
1
2
GAP-CLOSE-PWR-2U
1D05V_S0
1
C114
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1
C100
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
1
1
1
1
1
1
1
1
DY
2
2
C104
SCD1U10V2KX-4GP
C101
SCD1U10V2KX-4GP
C108
SCD1U10V2KX-4GP
C110
SCD1U10V2KX-4GP
C112
SCD1U10V2KX-4GP
C95
SCD1U10V2KX-4GP
C98
SCD1U10V2KX-4GP
C99
SC4D7U6D3V3KX-GP
1
2
C433
SC4D7U6D3V3KX-GP
layout note: "1D5V_VCCA_S0"
as short as possible
1D5V_S0
1D5V_VCCA_S0
L11
2
2
2
2
2
2
2
DY
2
DY
1
1
H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5
H_VID6
H_VID[6..0]
VCC_CORE
34
C421
SCD01U16V2KX-3GP
2
1
C427
SC10U6D3V5MX-3GP
PBY160808T-121Y-GP
DY
68.00206.021
2
2
1
2
R77
100R2F-L1-GP-U
TPAD30
TP24
2
VCC_SENSE 34
VSS_SENSE 34
1
TPAD30
TP26
TP94
TPAD30
Layout Note:
R88
100R2F-L1-GP-U
VCCSENSE and VSSSENSE lines
should be of equal length.
BGA479-SKT6-GPU6
62.10079.001
2
Layout Note:
Provide a test point (with
no stub) to connect a
differential probe
between VCCSENSE and
VSSSENSE at the location
where the two 54.9ohm
resistors terminate the
55 ohm transmission line.
1
TP151
TPAD30
TP23
TPAD30
BGA479-SKT6-GPU6
62.10079.001
1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
CPU (2 of 2)
Size
Document Number
Rev
Cathedral Peak
Date: Friday, May 16, 2008
A
B
C
D
-1
5
of
42
Sheet
E

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