Acer Aspire 4733z Quanta_ZQ5_RevB.pdf

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5
4
3
2
1
BOM MARK
IV@: INT VGA
EV@: STUFF FOR EXT VGA
SP@: STUFF FOR UMA or VGA
X'TAL
14.318MHz
DDR3 PWR
TPS51116
P40
CHARGER
ISL88731A
P36
THERMAL
PROTECTION
3/5V SYS PWR
P44
RT8206
P37
Penryn 478
D
CLOCK GENERATOR
ICS:
SELGO: SLG8SP513VTR
P2
uFCPGA
Thermal Sensor
(G780P81U)
P3
Fan Driver
(G991)
P25
DISCHARGER
P42
CPU CORE PWR
ISL6266A
P39
D
P3, P4
VGA CORE
MAX8792
FSB
667/800/1067 Mhz
EXT_LVDS
EXT_CRT
EXT_HDMI
+1.05V
P41
UP6111A
P38
ATI-Park
PCIE 16X
CRT
DDRIII
SO-DIMM 0
SO-DIMM 1
P16,P17
C
NB
Dual Channel DDR3
667/800 MHz
VRAM DDRIII
512MB
P18-P23
LVDS
RGB
SWITCH
LVDS
P24
Cantiga
(GM45/ PM45/ GL40)
P5, P6, P7, P8, P9, P10, P11
INT_LVDS
INT_CRT
CIRCUIT
HDMI
P25
P24
P25
C
INT_HDMI
HDMI switch
(PS8101T)
P25
HDD (SATA) *1
P26
X4 DMI interface
Ext USB Port x 2
USB 0,2
P27
SATA0
PCI-Express
PCIE-4
Mini Card
WLAN
P27
Int USB Port x 1
USB 6
P27
ODD (SATA)
P26
SATA1
USB 2.0
SB
ICH9M
P12,P13,P14,P15
Bluetooth
USB3
B
USB1
X'TAL
32.768KHz
P27
PCIE-6
CCD
USB11
Azalia
P24
X'TAL
25MHz
B
LPC
Media
Cardreader
(AU6437)
USB2
P30
Giga-LAN
BCM57780
P30
Audio CODEC
P28
(272)
EC (WPC781)
P33
X'TAL
32.768KHz
SPI ROM
A
Card Reader
Connector
Transformer
P32
P31
P33
Audio Amplifier
G1453L
P28
Int.
Speaker
P29
MIC Jack
P29
Int. MIC
P29
RJ45
P31
A
Touch Pad
P26
K/B COON.
P33
Size
Date:
Document Number
Block Diagram
Monday, July 12, 2010
1
Rev
1A
Sheet 1
of
43
5
4
3
2
5
4
3
2
1
+3V
+1.05V_VDD
L43
+1.05V
PBY160808T-301Y-N/2A/300ohm_6
C437
*0.1u/10V_4
D
PBY160808T-301Y-N/2A/300ohm_6
C544
+3V
L42
*0.1u/10V_4
C434
*0.1u/10V_4
C542
*10u/10V_8
C569
0.1u/10V_4
C557
0.1u/10V_4
C550
0.1u/10V_4
C450
0.1u/10V_4
C541
10u/10V_8
Modfiy it 5/4
C573
*10u/10V_8
C574
10u/10V_8
U15
C545
0.1u/10V_4
C568
0.1u/10V_4
C551
0.1u/10V_4
C546
0.1u/10V_4
C435
PM_STPPCI#
R313
R316
*2.2K_4
*2.2K_4
10K_4
10K_4
10K_4
10K_4
10K_4
5/7 Modfiy
PM_STPCPU#
02
D
0.1u/10V_4
CLK_PCIE_SRC11#
R322
SATA_CLKREQ#_R
R324
VDD_CK_VDD_REF
9
16
23
4
46
62
VDD_PCI
VDD_48
VDD_PLL3
VDD_REF
VDD_SRC
VDD_CPU
IO_VOUT
SCLK
SDA
55
7
6
45
44
61
60
58
57
54
53
42
41
40
39
37
38
51
50
48
47
34
35
31
32
28
29
24
25
20
21
63
R329
R331
10K_4
*10K_4
EV@10K_4
IV@10K_4
*10K_4
10K_4
PCLK_591_R
HIGH 27MHz
LOW SRC
PCLK_ICH_R
CLK_DREFSSCLK_R
CLK_DREFSSCLK#_R
CLK_DREFCLK_R
CLK_DREFCLK#_R
CK_PWRGD 14
+3V
PCLK_DEBUG_R
CLK_PCIE_SRC3
CLK_PCIE_SRC3#
R348
T97
CLK_PCIE_SATA 12
CLK_PCIE_SATA# 12
*EV@475/F_4
CLK_PCIE_SRC7
CLK_PCIE_SRC7#
T94
T93
CLK_PCIE_ICH 13
CLK_PCIE_ICH# 13
CLK_PCIE_LAN 31
CLK_PCIE_LAN# 31
PEG_CLKREQ# 19
CLK_MCH_OE#_C
R319
CLK_PCIE_SRC11#
R323
475/F_4
475/F_4
T91
T92
CLK_PCIE_3GPLL# 6
CLK_PCIE_3GPLL 6
CLK_MCH_OE# 6
MINI_CLKREQ# 28
CLK_PCIE_MINI1 28
CLK_PCIE_MINI1# 28
SMBCK1
SMBDT1
PM_STPPCI#
PM_STPCPU#
PM_STPPCI# 14
PM_STPCPU# 14
CLK_CPU_BCLK 3
CLK_CPU_BCLK# 3
CLK_MCH_BCLK 5
CLK_MCH_BCLK# 5
LAN_CLKREQ#_R
CLK_PCIE_SRC3
CLK_MCH_OE#_C
R320
R349
R317
CK505
+1.05V_VDD
SRC5/PCI_STOP#
SRC5#/CPU_STOP#
CPU0
CPU0#
CPU1
CPU1#
SRC8/ITP
SRC8#/ITP#
To SB
To CPU
To NB
19
27
33
52
43
56
VDD_96_IO
VDD_PLL3_IO
VDD_SRC_IO_1
VDD_SRC_IO_3
VDD_SRC_IO_2
VDD_CPU_IO
5/5 Add
For EMI
PCLK_591_R
C571
C581
C554
C578
*33p/50V_4
*15p/50V_4
*33p/50V_4
*33p/50V_4
C
14 SATACLKREQ#
31 LAN_CLKREQ#
28 PCLK_DEBUG
C
R321
R325
R330
T95
475/F_4
475/F_4
33_4
SATA_CLKREQ#_R
8
LAN_CLKREQ#_R
10
PCLK_DEBUG_R
PCI_CLK_SIO
PCI0/CR#_A
PCI1/CR#_B
PCI2/TME
PCI3
PCI4/SRC5_EN
PCIF5/ITP_EN
XTAL_IN
XTAL_OUT
USB_48/FSA
FSB/TEST/MODE
REF0/FSC/TESTSEL
VSS_BODY
VSS_PCI
VSS_48
VSS_IO
VSS_PLL3
VSS_CPU
VSS_SRC1
VSS_SRC2
VSS_SRC3
VSS_REF
SRC10#
SRC10
SRC11/CR#_H
SRC11#/CR#_G
SRC9
SRC9#
SRC7/CR#_F
SRC7#/CR#_E
SRC6
SRC6#
SRC4
SRC4#
SRC3/CR#_C
SRC3#/CR#_D
SRC2/SATA
SRC2#/SATA#
SRC1/SE1
SRC1#/SE2
SRC0/DOT96
SRC0#/DOT96#
CKPWRGD/PWRDWN#
SLG8SP513
To NB
CLKUSB_48
14M_ICH
11
12
13
14
3
2
35
13
PCLK_591
PCLK_ICH
R334
PCLK_ICH
R346
CG_XIN
CG_XOUT
R345
R337
CPU_BSEL0
R338
CPU_BSEL1
CPU_BSEL2
R314
R318
C549
33p/50V_4
33_4
33_4
PCLK_591_R
PCLK_ICH_R
To Mini Card 1 (WLAN)
PCLK_ICH_R
SEL2 SEL1
SEL0
Frequence select
CPU
100
133
166
200
266
333
400
SRC
100
100
100
100
100
100
100
PCI
33
33
33
33
33
33
33
Default
To ICH
To LAN
Modfiy it 5/4
FSC FSB FSA
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
1
1
1
0
0
0
0
1
33 CLK_Card48
14 CLKUSB_48
22_4
22_4
2.2K_4
10K_4
33_4
FSA
17
64
14
14M_ICH
FSC
CG_XIN
Y2
14.318MHZ
CL=20p
C548
33p/50V_4
B
CG_XOUT
5
65
15
18
22
26
59
30
36
49
1
To ICH
To NB or VGA
To NB or VGA
2
Reserved
B
1
SLG8SP513VTR ,ICS9LPRS365BKLFT
5/5 modify
ICS9LRS3165BKLFT
(ALPRS365000)
RTM875T-606
(AL000875000)
PCI2/TME
internal PD
PCI-3/SRC5_EN
internal PD
PCI-4/27M_SEL
internal PD
PCIF-5/ITP_EN
internal PD
PULL HIGH
PULL DOWN
+3V
Pin 11
PCI2/TME
NO OVERCLOCKING (default)
NORMAL RUN
PIN37/38 IS
PCI_STOP/CPU_STOP
PIN 17/18
IS SRC/DOT
+3V
(default)
R336
R332
R342
R343
From GMCH
RN15
CLK_DREFCLK_R
CLK_DREFCLK#_R
RN14
CLK_DREFSSCLK_R
CLK_DREFSSCLK#_R
3
1
3
1
4
2
4
2
2
4
RN9
IV@0_4P2R
IV@0_4P2R
CLK_DREFCLK 6
CLK_DREFCLK# 6
CLK_DREFSSCLK 6
CLK_DREFSSCLK# 6
CLK_PCIE_VGA 18
CLK_PCIE_VGA# 18
27M_NONSS 19
Pin 12
PCI-3
PIN37/38 IS SRC5
To NB
(default)
3 CPU_BSEL0
3 CPU_BSEL1
3 CPU_BSEL2
R347
R267
R315
+3V
0_4
0_4
0_4
RN10
1
CLK_DREFCLK_R
3
CLK_DREFCLK#_R
EV@0_4P2R
Pin 13
PCI-4/27M_SEL
PIN 17/18 IS 27MHz
From Deisceret
MCH_BSEL0 6
MCH_BSEL1 6
MCH_BSEL2 6
CLK_DREFSSCLK_R
1
CLK_DREFSSCLK#_R
3
2
4
*EV@33_4P2R
Pin 14
PCIF-5/ITP_EN
PIN 46/47 IS CPUITP
PIN 46/47 IS SRC8
(default)
5/18 Modify
+3V
5/22 modify
A
2
Q13
14,16,28 PDAT_SMB
Q12
3
2N7002E
REV:B 6/12
1
SMBDT1
14,16,28 PCLK_SMB
3
2N7002E
2
R258
4.7K_4
<MAIN>:ICS9LRS3165BKLFT QCI:ALPRS365000
<SECOND>:SLG8SP513VTR QCI:AL8SP513000
<SECOND>:RTM875N-606-VD-GRT QCI:AL000875000
R259
4.7K_4
A
1
SMBCK1
Size
REV:B 6/11
Date:
5
4
3
2
Document Number
CLOCK GENERATOR
Monday, July 12, 2010
1
Rev
1A
Sheet 2
of
43
5
4
3
2
1
5
H_A#[3..16]
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
J4
L5
L4
K5
M3
N2
J1
N3
P5
P2
L2
P4
P1
R1
M1
K3
H2
K2
J3
L1
Y2
U5
R3
W6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
U2
V4
W3
AA4
AB2
AA3
V1
A6
A5
C4
D5
C6
B4
A3
M4
N5
T2
V3
B2
D2
D22
D3
F6
U17A
A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#
ADS#
BNR#
BPRI#
DEFER#
DRDY#
DBSY#
BR0#
H1
E2
G5
H5
F21
E1
F1
D20
B3
H4
C1
F3
F4
G3
G2
G6
E4
AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20
XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
SYS_RST#
T56
T86
T88
T55
T89
H_IERR#
R245
56_4
H_ADS# 5
H_BNR# 5
H_BPRI# 5
H_DEFER# 5
H_DRDY# 5
H_DBSY# 5
H_BREQ# 5
+1.05V
H_INIT# 12
H_LOCK# 5
H_CPURST# 5
H_RS#0 5
H_RS#1 5
H_RS#2 5
H_TRDY# 5
H_HIT# 5
H_HITM# 5
5
H_D#[0..15]
H_D#[0..15]
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
E22
F24
E26
G22
F23
G25
E25
E23
K24
G24
J24
J23
H22
F26
K22
H23
J26
H26
H25
N22
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
L26
M26
N24
U17B
D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#
D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#
GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
BSEL[0]
BSEL[1]
BSEL[2]
Penryn
D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#
D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#
COMP[0]
COMP[1]
COMP[2]
COMP[3]
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PSI#
Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22
AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20
R26
U26
AA1
Y1
E5
B5
D24
D6
D7
AE6
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#[32..47]
H_D#[32..47]
5
03
D
CONTROL
D
IERR#
INIT#
LOCK#
5 H_ADSTB#0
5 H_REQ#[0..4]
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#
A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#
RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#
HIT#
HITM#
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
DBR#
5
5
5
5
H_DSTBN#0
H_DSTBP#0
H_DINV#0
H_D#[16..31]
H_D#[16..31]
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
DATA GRP 2
ADDR GROUP_0
ADDR GROUP_0
DATA GRP 0
DATA GRP 0
H_DSTBN#2 5
H_DSTBP#2 5
H_DINV#2 5
H_D#[48..63]
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_D#[48..63]
5
5
H_A#[17..35]
XDP/ITP SIGNALS
Connect it to CPU DBR# is for ITP debug port
or CPU interposer (like ICE) to reset the system
SYS_RST# 14
+1.05V
DATA GRP 3
ADDR GROUP_1
ADDR GROUP_1
Layout note:
comp0,2: Zo=27.4ohm, L<0.5"
comp1,3: Zo=55ohm, L<0.5"
Layout note:
DPRSTP# , Daisy Chain
(SB>Power>NB>CPU)
H_DSTBN#3 5
H_DSTBP#3 5
H_DINV#3 5
C
DATA GRP 1
THERMAL
PROCHOT#
THERMDA
THERMDC
THERMTRIP#
D21
A24
B25
C7
H_PROCHOT#_D
H_THERMDA
H_THERMDC
PM_THRMTRIP#
R311
1K/F_4
5
5
5
H_DSTBN#1
H_DSTBP#1
H_DINV#1
T108
T112
T125
T90
T87
T126
T127
2
2
2
CPU_BSEL0
CPU_BSEL1
CPU_BSEL2
C
5
H_ADSTB#1
12 H_A20M#
12 H_FERR#
12 H_IGNNE#
12
12
12
12
H_STPCLK#
H_INTR
H_NMI
H_SMI#
A20M#
FERR#
IGNNE#
STPCLK#
LINT0
LINT1
SMI#
RSVD[01]
RSVD[02]
RSVD[03]
RSVD[04]
RSVD[05]
RSVD[06]
RSVD[07]
RSVD[08]
RSVD[09]
H CLK
BCLK[0]
BCLK[1]
A22
A21
CLK_CPU_BCLK 2
CLK_CPU_BCLK# 2
R312
2K/F_4
H_GTLREF
AD26
CPU_TEST1
C23
CPU_TEST2
D25
CPU_TEST3
C24
CPU_TEST4
AF26
AF1
CPU_TEST5
A26
CPU_TEST6
C3
CPU_TEST7
B22
B23
C21
MISC
COMP0
COMP1
COMP2
COMP3
R344
R328
R257
R254
27.4/F_6
54.9/F_4
27.4/F_6
54.9/F_4
ICH_DPRSTP# 6,12,39
H_DPSLP# 12
H_DPWR# 5
H_PWRGD 12
H_CPUSLP# 5
PSI#
39
RESERVED
ICH
Layout note:
H_GTLREF: Zo=55 ohm
L<0.5", 2/3*VCCP+-2%
Penryn
B
Thermal Trip
2
+1.05V
+1.05V
3
CPU Thermal monitor
Q18
B
+3V
XDP PU/PD
+3V
R400
SYS_RST#
R391
*1K_4
+1.05V
200_6
6,14,39 DELAY_VR_PWRGOOD
DMN601K-7
VCC_TH
1
C624
XDP_TDO
R398
56_4
6,12 PM_THRMTRIP#
PM_THRMTRIP#
1
2
Q17
3
MMBT3904
U21
SYS_SHDN#
37,44
35 2ND_MBCLK
35 2ND_MBDATA
H_THERMDA
8
7
6
SCLK
SDA
ALERT#
OVERT#
VCC
DXP
DXN
GND
1
2
3
5
C621
2200p_4
H_THERMDC
XDP_BPM#5
XDP_TCK
XDP_TRST#
R310
R265
R266
54.9/F_4
54.9/F_4
54.9/F_4
0.1U/10V_4
XDP_TDI
XDP_TMS
R260
R264
54.9/F_4
54.9/F_4
R261
*54.9/F_4
ZR6 hang up issue
Processor hot
+1.05V
A
No use Thermal trip CPU side still PU 56ohm.
Use Thermal trip can share PU at SB side
No use PROCHOT CPU side still PU 56ohm.
Use PROCHOT to optional receiver CPU side PU
68ohm and through isolat 2.2K ohm to receiver
side
R274
*0_4
14 THERM_ALERT#
4
+3V
R401
R395
R394
*10K_4
*0_4
10K_4
G780P81U(MSOP-8)
XDP_DBRESET# and XDP_TDO
reserve for XDP
A
R273
56_4
H_PROCHOT#_D
+3V
27 THER_OVERT#
GMT
AL000780000
AL095245000
AL83L771K01
2
Use 2200p
Use 2200p
Use 2200p
Size
Date:
Document Number
4/20 Modify
H_PROCHOT# 39
NS
WINDBOND
CPU Host Bus
Monday, July 12, 2010
1
Rev
1A
Sheet 3
of
43
5
4
3
5
4
3
2
1
U17D
VCC_CORE
VCC_CORE
U17C
D
C
B
A
A4
A8
A11
A14
A16
A19
A23
AF2
B6
B8
B11
B13
B16
B19
B21
B24
C5
C8
C11
C14
C16
C19
C2
C22
C25
D1
D4
D8
D11
D13
D16
D19
D23
D26
E3
E6
E8
E11
E14
E16
E19
E21
E24
F5
F8
F11
F13
F16
F19
F2
F22
F25
G4
G1
G23
G26
H3
H6
H21
H24
J2
J5
J22
J25
K1
K4
K23
K26
L3
L6
L21
L24
M2
M5
M22
M25
N1
N4
N23
N26
P3
VSS[001]
VSS[002]
VSS[003]
VSS[004]
VSS[005]
VSS[006]
VSS[007]
VSS[008]
VSS[009]
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]
VSS[017]
VSS[018]
VSS[019]
VSS[020]
VSS[021]
VSS[022]
VSS[023]
VSS[024]
VSS[025]
VSS[026]
VSS[027]
VSS[028]
VSS[029]
VSS[030]
VSS[031]
VSS[032]
VSS[033]
VSS[034]
VSS[035]
VSS[036]
VSS[037]
VSS[038]
VSS[039]
VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]
VSS[045]
VSS[046]
VSS[047]
VSS[048]
VSS[049]
VSS[050]
VSS[051]
VSS[052]
VSS[053]
VSS[054]
VSS[055]
VSS[056]
VSS[057]
VSS[058]
VSS[059]
VSS[060]
VSS[061]
VSS[062]
VSS[063]
VSS[064]
VSS[065]
VSS[066]
VSS[067]
VSS[068]
VSS[069]
VSS[070]
VSS[071]
VSS[072]
VSS[073]
VSS[074]
VSS[075]
VSS[076]
VSS[077]
VSS[078]
VSS[079]
VSS[080]
VSS[081]
Penryn
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25
VCC:38A (Low power type)
VCC:47A (Standard type)
04
D
C470
*10U/6.3V_8
C445
10U/6.3V_8
C447
10U/6.3V_8
C444
*10U/6.3V_8
C471
10U/6.3V_8
C564
*10U/6.3V_8
C563
*10U/6.3V_8
C424
*10U/6.3V_8
C562
10U/6.3V_8
C590
*10U/6.3V_8
C589
10U/6.3V_8
C588
*10U/6.3V_8
C468
*10U/6.3V_8
C466
10U/6.3V_8
C429
*10U/6.3V_8
C465
*10U/6.3V_8
C442
*10U/6.3V_8
C441
*10U/6.3V_8
C472
*10U/6.3V_8
C433
10U/6.3V_8
C419
10U/6.3V_8
Layout Note:
Place these parts
reference to Intel demo
board.
C446
*10U/6.3V_8
C443
*10U/6.3V_8
C420
10U/6.3V_8
C425
*10U/6.3V_8
C421
*10U/6.3V_8
C422
10U/6.3V_8
C423
*10U/6.3V_8
C567
10U/6.3V_8
C566
*10U/6.3V_8
C565
10U/6.3V_8
C591
10U/6.3V_8
C587
10U/6.3V_8
C586
*10U/6.3V_8
C469
10U/6.3V_8
C467
*10U/6.3V_8
A7
A9
A10
A12
A13
A15
A17
A18
A20
B7
B9
B10
B12
B14
B15
B17
B18
B20
C9
C10
C12
C13
C15
C17
C18
D9
D10
D12
D14
D15
D17
D18
E7
E9
E10
E12
E13
E15
E17
E18
E20
F7
F9
F10
F12
F14
F15
F17
F18
F20
AA7
AA9
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AB9
AC10
AB10
AB12
AB14
AB15
AB17
AB18
VCC[001]
VCC[002]
VCC[003]
VCC[004]
VCC[005]
VCC[006]
VCC[007]
VCC[008]
VCC[009]
VCC[010]
VCC[011]
VCC[012]
VCC[013]
VCC[014]
VCC[015]
VCC[016]
VCC[017]
VCC[018]
VCC[019]
VCC[020]
VCC[021]
VCC[022]
VCC[023]
VCC[024]
VCC[025]
VCC[026]
VCC[027]
VCC[028]
VCC[029]
VCC[030]
VCC[031]
VCC[032]
VCC[033]
VCC[034]
VCC[035]
VCC[036]
VCC[037]
VCC[038]
VCC[039]
VCC[040]
VCC[041]
VCC[042]
VCC[043]
VCC[044]
VCC[045]
VCC[046]
VCC[047]
VCC[048]
VCC[049]
VCC[050]
VCC[051]
VCC[052]
VCC[053]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]
VCC[065]
VCC[066]
VCC[067]
Penryn
VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]
VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]
VCCA[01]
VCCA[02]
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
VCCSENSE
VSSSENSE
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
B26
C26
AD6
AF5
AE5
AF4
AE3
AF3
AE2
AF7
AE7
Layout Note:
Inside CPU center cavity in 2 rows
VCCP : 2.5A(Supply after VCC Stable)
4.5A(Supply before VCC Stable)
+1.05V
C428
0.1U/10V_4
C431
0.1U/10V_4
C438
+
C622
0.1U/10V_4
330U/2V_7343
C
C426
*0.1U/10V_4
C432
0.1U/10V_4
C440
0.1U/10V_4
VCCA:130mA
+1.5V
B
H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5
H_VID6
39
39
39
39
39
39
39
C599
0.01U/25V_4
C598
10U/6.3V_8
R308
100/F_6
VCC_CORE
VCCSENSE 39
VSSSENSE 39
R309
100/F_6
+
C491
*330U/2V_7343
+
C580
330U/2V_7343
+
C430
330U/2V_7343
+
C623
*330U/2V_7343
Layout Note:
Z0=27.4,PU/PD L<1"
A
Montevina platform : Early Reference Board Schematics Feb 2007. Rev 1.0
stuff 22U*34, NC 22U*2
stuff 330U*2, NC330U*2
5
4
3
2
Size
Date:
Document Number
CPU Power
Monday, July 12, 2010
1
Rev
1A
Sheet
4
of
43
5
4
3
2
1
3
H_D#[0..63]
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_SWING
H_RCOMP
U20A
H_A#[3..35]
3
QCI P/N
Intel Cantiga (G)M
D
AJSLB940T04
AJSLB970T06
Intel Cantiga (P)M
Intel Cantiga (G)L A1
AJSLGGM0T04
C
+1.05V
R411
221/F_4
0.3125*VCCP
WIDE(10):SPACING(20) ,
L<0.5"
H_SWING
R410
100/F_4
C642
0.1U/10V_4
B
H_RCOMP
R407
24.9/F_4
Layout Note:
WIDE(10):SPACING(20) ,
L<0.5"
F2
G8
F8
E6
G2
H6
H2
F6
D4
H3
M9
M11
J1
J2
N12
J6
P2
L2
R2
N9
L6
M5
J3
N2
R1
N5
N6
P13
N8
L7
N10
M3
Y3
AD14
Y6
Y10
Y12
Y14
Y7
W2
AA8
Y9
AA13
AA9
AA11
AD11
AD10
AD13
AE12
AE9
AA2
AD8
AA3
AD3
AD7
AE14
AF3
AC1
AE3
AC3
AE11
AE8
AG2
AD6
C5
E3
H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63
H_SWING
H_RCOMP
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35
H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_BNR#
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
A14
C15
F16
H13
C18
M16
J13
P16
R16
N17
M13
E17
P17
F17
G20
B19
J16
E20
H16
J20
L17
A17
B17
L16
C21
J17
H20
B18
K17
B20
F21
K21
L20
H12
B16
G17
A9
F11
G12
E9
B10
AH7
AH6
J11
F9
H9
E12
H11
C9
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADS#
3
H_ADSTB#0 3
H_ADSTB#1 3
H_BNR#
3
H_BPRI# 3
H_BREQ# 3
H_DEFER# 3
H_DBSY# 3
CLK_MCH_BCLK 2
CLK_MCH_BCLK# 2
H_DPWR# 3
H_DRDY# 3
H_HIT#
3
H_HITM# 3
H_LOCK# 3
H_TRDY# 3
05
D
C
HOST
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
H_RS#_0
H_RS#_1
H_RS#_2
J8
L3
Y13
Y1
L10
M7
AA5
AE6
L9
M8
AA6
AE5
B15
K13
F13
B13
B14
B6
F12
C8
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
H_DINV#[3..0]
3
B
H_DSTBN#[3..0]
3
H_DSTBP#[3..0]
3
+1.05V
H_REQ#[0..4]
3
R414
A
2/3*VCCP
WIDE(10):SPACING(20),
L<0.5"
3
3
H_CPURST#
H_CPUSLP#
C12
E11
H_CPURST#
H_CPUSLP#
H_RS#[0..2]
3
1K/F_4
H_AVREF
R415
2K/F_4
C649
*0.1U/10V_4
A11
B11
H_AVREF
H_DVREF
CANTIGA_PM
A
Size
Date:
5
4
3
2
Document Number
GMCH HOST
Monday, July 12, 2010
1
Rev
1A
Sheet 5
of
43

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