Acer Aspire 5750 5750G Gateway NV57H - Compal_LA-6901P.pdf

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A
B
C
D
E
Compal Confidential
1
Model Name : P5WE0
File Name : LA-6901P
BOM P/N:43
1
2
p.
su
/x
Compal Confidential
/
2
P5WE0 M/B Schematics Document
Intel Sandy Bridge Processor with DDRIII + Cougar Point PCH
Nvidia N12P GS/GV
3
:/
/m
2010-08-11
REV:0.1
yc
om
3
4
h
tt
p
4
Security Classification
Compal Secret Data
2010/08/11
Deciphered Date
Compal Electronics, Inc.
2011/08/11
Title
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Cover Page
Size Document Number
Custom
Date:
Rev
Sheet
E
0.1
P5WE0 M/B LA-6901P Schematic
1
of
Friday, August 27, 2010
59
B
C
D
A
B
C
D
E
Fan Control
page 38
1
1
PEG(DIS)
Nvidia
N12P GS/GV
page23~31
100MHz
PCI-E 2.0x16 5GT/s PER LANE
133MHz
Intel
Sandy Bridge
Processor
Memory BUS(DDRIII)
204pin DDRIII-SO-DIMM X2
Dual Channel
BANK 0, 1, 2, 3
1.5V DDRIII 1066/1333
page 12,13
rPGA989
page 5~11
/
HDMI(DIS)
CRT(DIS)
CRT Conn.
page 33
LVDS(DIS)
p.
su
/x
FDI x8
100MHz
DMI x4
100MHz
1GB/s x4
USB 2.0 conn x2
USB port 0,1 on
USB/B
page 39
3.3V 48MHz
Bluetooth
Conn
USB port 13
page 39
CMOS Camera
USB port 10
page 32
3G connector
USB port 9,12 on 3G/B
page 32
2
HDMI Conn.
page 34
2
LVDS Conn.
page 32
2.7GT/s
LVDS(UMA/OPTIMUS)
CRT(UMA/OPTIMUS)
TMDS(UMA/OPTIMUS)
PCI-Express x 8 (ARD PCIE2.0 2.5GT/s)
100MHz
100MHz
USBx14
Intel
Cougar Point-M
HD Audio
3.3V 24MHz
yc
om
PCH
HDA Codec
ALC271X/277X
port 5
port 2,3
port 1
SATA x 6 (GEN1 1.5GT/S ,GEN2 3GT/S)
989pin BGA
page 14~22
SPI
page 43
USB 3.0 conn x1
page 45
MINI Card x2
WLAN, WWAN
USB port 12,13
page 38
LAN(GbE) &
Card Reader
BCM57785
page 36
:/
/m
SPI ROM x1
page 14
Int. Speaker
page 44
Phone Jack x 2
page 44
port 0,1
3
port 2
Card Reader
Conn.
page
RJ45
page 37
SATA HDD
Conn.
page
35
SATA CDROM
Conn.
page 35
LPC BUS
33MHz
3
37
tt
p
Sub-board
LS-6901P
ENE KB930
page 40
h
RTC CKT.
page 14
USB 2.0/B 2Port
USB Port0,1
page 39
LF-6901P
FPC for USB3.0
CPU XDP
Touch Pad
page 41
Int.KBD
page 41
page 6
LS-6902P
Power On/Off CKT.
page 42
PWR/B
page 39
PCH XDP
BIOS ROM
DC/DC Interface CKT.
4
page 14
LS-6903P
3G/B
page 41
page 40
4
page 46
Power Circuit DC/DC
page 48~56
LS-6904P
USB 3.0 /B
1 port as USB3.0
1 port as USB2.0
Security Classification
Compal Secret Data
2010/08/11
Deciphered Date
Compal Electronics, Inc.
2011/08/11
Title
Issued Date
page 41
B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
Block Diagrams
Size Document Number
Custom
Date:
P5WE0 M/B LA-6901P Schematic
Friday, August 27, 2010
E
Rev
0.1
Sheet
A
2
of
59
D
A
B
C
D
E
Voltage Rails
Power Plane
VIN
SIGNAL
Description
Adapter power supply (19V)
S1
N/A
N/A
N/A
ON
ON
ON
ON
ON
ON
ON
ON
ON
S3
N/A
N/A
N/A
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON
OFF
S5
N/A
N/A
N/A
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
STATE
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
SLP_S1# SLP_S3#
SLP_S4# SLP_S5#
+VALW
+V
+VS
Clock
HIGH
LOW
LOW
LOW
LOW
HIGH
HIGH
LOW
LOW
LOW
HIGH
HIGH
HIGH
LOW
LOW
HIGH
HIGH
HIGH
HIGH
LOW
ON
ON
ON
ON
ON
ON
ON
ON
OFF
OFF
ON
ON
OFF
OFF
OFF
ON
LOW
OFF
OFF
OFF
1
BATT+
B+
1
Battery power supply (12.6V)
AC or battery power rail for power circuit.
Core voltage for CPU
+CPU_CORE
+VGA_CORE
+VGFX_CORE
+0.75VS
Core voltage for GPU
Core voltage for UMA graphic
+0.75VP to +0.75VS switched power rail for DDR terminator
+1.05VSDGPU
+1.05VS_VTT
+1.0VSPDGPU to +1.0VSDGPU switched power rail for GPU
+1.05VS_VCCPP to +1.05VS_VCCP switched power rail for CPU
+1.05VS_PCH
+1.5V
+1.5VS
+1.05VS_VCCP to +1.05VS_PCH power for PCH
+1.5VP to +1.5V power rail for DDRIII
+1.5V to +1.5VS switched power rail
Board ID / SKU ID Table for AD channel
Vcc
Ra/Rc/Re
Board ID
+1.5VSDGPU
+1.8VS
+1.5VS to +1.5VSDGPU switched power rail for GPU
(+5VALW or +3VALW) to 1.8V switched power rail to PCH & GPU
ON
ON
OFF
OFF
OFF
OFF
+1.8VSDGPU
+3VALW
+1.8VS to +1.8VSDGPU switched power rail for GPU
+3VALW always on power rail
ON
ON
OFF
ON
OFF
ON*
+3VALW_EC
+3V_LAN
+3VALW_PCH
2
+3VALW always to KBC
+3VALW to +3V_LAN power rail for LAN
+3VALW to +3VALW_PCH power rail for PCH (Short Jumper)
ON
ON
ON
ON
ON
ON
ON
ON
OFF
ON
ON*
ON*
ON*
OFF
ON*
p.
su
/x
+3VS
+5VALW
+3VALW to +3VS power rail
+5VALWP to +5VALW power rail
+5VALW to +5VALW_PCH power rail for PCH (Short resister)
+5VALW to +5VS switched power rail
+VSBP to +VSB always on power rail for sequence control
RTC power
0
1
2
3
4
5
6
7
3.3V +/- 5%
100K +/- 5%
Rb / Rd / Rf
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
NC
V
AD_BID
min
0 V
0.216 V
0.436 V
0.712 V
1.036 V
1.453 V
1.935 V
2.500 V
V
AD_BID
typ
0 V
0.250 V
0.503 V
0.819 V
1.185 V
1.650 V
2.200 V
3.300 V
V
AD_BID
max
0 V
0.289 V
0.538 V
0.875 V
1.264 V
1.759 V
2.341 V
3.300 V
EVT
DVT
PVT
Pre-MP
2
+5VALW_PCH
ON
ON
ON*
OFF
ON*
ON
+5VS
+VSB
+RTCVCC
ON
ON
ON
OFF
ON
ON
BOARD ID Table
/
BTO Option Table
BTO Item
UMA Only
UMA with OPTIMUS
Dis with OPTIMUS
DIS Only
OPTIMUS
Non-OPTIMUS
3G
Blue Tooth
USB2.0
USB3.0
VRAM
Connector
Unpop
LAN Chip A0 version
LAN Chip B0 version
BOM Structure
UMAO@
UMA@
DIS@
DISO@
OPT@
NOPT@
3G@
BT@
USB20@
USB30@
X76@
CONN@
@
A0@
B0@
yc
om
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
EC SM Bus1 address
Device
Smart Battery
EC SM Bus2 address
Device
Address
Address
0001 011X b
PCH SM Bus address
3
:/
/m
Board ID
0
1
2
3
4
5
6
7
PCB Revision
0.1
0.2
0.3
1.0
Device
Clock Generator (9LVS3199AKLFT,
RTM890N-631-VB-GRT)
DDR DIMM0
DDR DIMM2
Address
1101 0010b
1001 000Xb
1001 010Xb
3
USB Port Table
USB 2.0 USB 1.1 Port
3 External
USB Port
USB/B (Right Side)
USB/B (Right Side)
USB 2.0 & USB3.0 Conn.
tt
p
UHCI0
UHCI1
EHCI1
UHCI2
UHCI3
3G & BT & USB30 & USB20 Config
USB30 SKU:
USB30@
3G SKU:
3G@
BT SKU:
BT@
USB20 SKU:
USB20@
LAN Chip A0 version:
A0@
LAN chip B0 Version:
B0@
OPTMIUS SKU:
OPT@
Non-OPTMIUS SKU:
NOPT@
4
BOM Config
BT@/3G@/USB30@/UMA@/UMAO@/NOPT@/A0@
UMA Only:
BT@/3G@/USB30@/UMA@/DIS@/X76@/OPT@/A0@
OPTIMUS:
BT@/3G@/USB30@/DISO@/DIS@/X76@/NOPT@/A0@
DIS Only:
VRAM BOM Config
X76***BOL01:
X76***BOL02:
Samsung
Hynix
UHCI4
EHCI2
UHCI5
UHCI6
0
1
2
3
4
5
6
7
8
9
10
11
12
13
h
Mini Card 1(WLAN)
3G/B(WWAN)
Camera
Mini Card 2(Reserved)
SIM Card (3G/B)
Blue Tooth
Compal Secret Data
4
VRAM P/N :
Samsung : SA000035700 (S IC D3 64MX16 K4W1G1646E-HC12 FBGA 96P)
Hynix : SA000032400 (S IC D3 64MX16 H5TQ1G63BFR-12C FBGA 1.5V )
Security Classification
Compal Electronics, Inc.
2011/08/11
Title
Issued Date
2010/08/11
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Notes List
Size Document Number
Custom
Date:
P5WE0 M/B LA-6901P Schematic
Friday, August 27, 2010
E
Rev
0.1
Sheet
3
of
59
B
C
D
5
4
3
2
1
+1.05VS_VTT
R517
24.9_0402_1%
D
15
15
15
15
15
15
15
15
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
B27
B25
A25
B24
DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
J22
J21
H22
PEG_COMP
2
JCPU1A
PEG_ICOMPI and PEG_RCOMPO signals should be
shorted and routed,
max length = 500 mils,trace width=4mils
PEG_ICOMPO signals should be routed with - max
length = 500 mils,trace width=12mils
spacing =15mils
1
D
DMI
B28
B26
A24
B23
DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]
15
15
15
15
15
15
15
15
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
G21
E22
F21
D21
DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]
PCI EXPRESS* - GRAPHICS
C
Intel(R) FDI
15
15
15
15
15
15
15
15
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
A21
H19
E19
F18
B21
C20
D18
E17
FDI0_TX#[0]
FDI0_TX#[1]
FDI0_TX#[2]
FDI0_TX#[3]
FDI1_TX#[0]
FDI1_TX#[1]
FDI1_TX#[2]
FDI1_TX#[3]
+1.05VS_VTT
15 FDI_FSYNC0
15 FDI_FSYNC1
J18
J17
FDI0_FSYNC
FDI1_FSYNC
R145
24.9_0402_1%
EDP_COMP
:/
/m
eDP_COMPIO and ICOMPO signals should
be shorted near balls,
Trace Width for EDP_COMPIO=4mils,
EDP_ICOMPO=12mils,
and both length less than 500 mils...
should not be left floating
,even if disable eDP function...
B
15 FDI_INT
H20
FDI_INT
15 FDI_LSYNC0
15 FDI_LSYNC1
J19
H17
FDI0_LSYNC
FDI1_LSYNC
2
A18
A17
B16
yc
om
15
15
15
15
15
15
15
15
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
A22
G19
E20
G18
B20
C19
D19
F17
FDI0_TX[0]
FDI0_TX[1]
FDI0_TX[2]
FDI0_TX[3]
FDI1_TX[0]
FDI1_TX[1]
FDI1_TX[2]
FDI1_TX[3]
PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
p.
su
/x
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
eDP_COMPIO
eDP_ICOMPO
eDP_HPD
tt
p
C17
F16
C16
G15
h
eDP_TX[0]
eDP_TX[1]
eDP_TX[2]
eDP_TX[3]
C18
E16
D16
F15
eDP_TX#[0]
eDP_TX#[1]
eDP_TX#[2]
eDP_TX#[3]
Sandy Bridge_rPGA_Rev0p61
CONN@
eDP
C15
D15
eDP_AUX
eDP_AUX#
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
PEG_GTX_C_HRX_P15
J33
PEG_GTX_C_HRX_P14
L35
PEG_GTX_C_HRX_P13
K34
PEG_GTX_C_HRX_P12
H35
PEG_GTX_C_HRX_P11
H32
PEG_GTX_C_HRX_P10
G34
PEG_GTX_C_HRX_P9
G31
PEG_GTX_C_HRX_P8
F33
PEG_GTX_C_HRX_P7
F30
PEG_GTX_C_HRX_P6
E35
PEG_GTX_C_HRX_P5
E33
PEG_GTX_C_HRX_P4
F32
PEG_GTX_C_HRX_P3
D34
PEG_GTX_C_HRX_P2
E31
PEG_GTX_C_HRX_P1
C33
PEG_GTX_C_HRX_P0
B32
PEG_HTX_GRX_N15
M29
PEG_HTX_GRX_N14
M32
PEG_HTX_GRX_N13
M31
PEG_HTX_GRX_N12
L32
PEG_HTX_GRX_N11
L29
PEG_HTX_GRX_N10
K31
PEG_HTX_GRX_N9
K28
PEG_HTX_GRX_N8
J30
PEG_HTX_GRX_N7
J28
PEG_HTX_GRX_N6
H29
PEG_HTX_GRX_N5
G27
PEG_HTX_GRX_N4
E29
PEG_HTX_GRX_N3
F27
PEG_HTX_GRX_N2
D28
PEG_HTX_GRX_N1
F26
PEG_HTX_GRX_N0
E25
PEG_HTX_GRX_P15
M28
PEG_HTX_GRX_P14
M33
PEG_HTX_GRX_P13
M30
PEG_HTX_GRX_P12
L31
PEG_HTX_GRX_P11
L28
PEG_HTX_GRX_P10
K30
PEG_HTX_GRX_P9
K27
PEG_HTX_GRX_P8
J29
PEG_HTX_GRX_P7
J27
PEG_HTX_GRX_P6
H28
PEG_HTX_GRX_P5
PEG_HTX_GRX_P4
G28
E28
PEG_HTX_GRX_P3
F28
PEG_HTX_GRX_P2
D27
PEG_HTX_GRX_P1
E26
PEG_HTX_GRX_P0
D25
/
G22
D22
F20
C21
DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]
PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
K33
PEG_GTX_C_HRX_N15
PEG_GTX_C_HRX_N14
M35
L34
PEG_GTX_C_HRX_N13
PEG_GTX_C_HRX_N12
J35
PEG_GTX_C_HRX_N11
J32
PEG_GTX_C_HRX_N10
H34
PEG_GTX_C_HRX_N9
H31
PEG_GTX_C_HRX_N8
G33
PEG_GTX_C_HRX_N7
G30
PEG_GTX_C_HRX_N6
F35
PEG_GTX_C_HRX_N5
E34
PEG_GTX_C_HRX_N4
E32
PEG_GTX_C_HRX_N3
D33
PEG_GTX_C_HRX_N2
D31
PEG_GTX_C_HRX_N1
B33
PEG_GTX_C_HRX_N0
C32
C46
1
2
DIS@
0.22U_0402_10V6K
PEG_GTX_HRX_N15
PEG_GTX_HRX_N14
C49
1
2
DIS@
0.22U_0402_10V6K
PEG_GTX_HRX_N13
C51
1
2
DIS@
0.22U_0402_10V6K
PEG_GTX_HRX_N12
C53
1
2
DIS@
0.22U_0402_10V6K
PEG_GTX_HRX_N11
C60
1
2
DIS@
0.22U_0402_10V6K
PEG_GTX_HRX_N10
C71
1
2
DIS@
0.22U_0402_10V6K
PEG_GTX_HRX_N9
C75
1
2
DIS@
0.22U_0402_10V6K
PEG_GTX_HRX_N8
C82
1
2
DIS@
0.22U_0402_10V6K
PEG_GTX_HRX_N7
C92
1
2
DIS@
0.22U_0402_10V6K
C93
1
2
DIS@
0.22U_0402_10V6K
PEG_GTX_HRX_N6
PEG_GTX_HRX_N5
C102
1
2
DIS@
0.22U_0402_10V6K
PEG_GTX_HRX_N4
C111
1
2
DIS@
0.22U_0402_10V6K
PEG_GTX_HRX_N3
C113
1
2
DIS@
0.22U_0402_10V6K
PEG_GTX_HRX_N2
C125
1
2
DIS@
0.22U_0402_10V6K
PEG_GTX_HRX_N1
C129
1
2
DIS@
0.22U_0402_10V6K
PEG_GTX_HRX_N0
C144
1
2
DIS@
0.22U_0402_10V6K
PEG_GTX_HRX_P15
C47
1
2
DIS@
0.22U_0402_10V6K
PEG_GTX_HRX_P14
C50
1
2
DIS@
0.22U_0402_10V6K
PEG_GTX_HRX_P13
C52
1
2
DIS@
0.22U_0402_10V6K
PEG_GTX_HRX_P12
C56
1
2
DIS@
0.22U_0402_10V6K
PEG_GTX_HRX_P11
C66
1
2
DIS@
0.22U_0402_10V6K
PEG_GTX_HRX_P10
C68
1
2
DIS@
0.22U_0402_10V6K
PEG_GTX_HRX_P9
C81
1
2
DIS@
0.22U_0402_10V6K
PEG_GTX_HRX_P8
C86
1
PEG_GTX_HRX_P7
2
DIS@
0.22U_0402_10V6K
C89
1
PEG_GTX_HRX_P6
2
DIS@
0.22U_0402_10V6K
C100
1
2
DIS@
0.22U_0402_10V6K
PEG_GTX_HRX_P5
PEG_GTX_HRX_P4
C105
1
2
DIS@
0.22U_0402_10V6K
PEG_GTX_HRX_P3
C106
1
2
DIS@
0.22U_0402_10V6K
PEG_GTX_HRX_P2
C117
1
2
DIS@
0.22U_0402_10V6K
PEG_GTX_HRX_P1
C119
1
2
DIS@
0.22U_0402_10V6K
PEG_GTX_HRX_P0
C135
1
2
DIS@
0.22U_0402_10V6K
C138
1
2
DIS@
0.22U_0402_10V6K
PEG_HTX_C_GRX_N15
C516
1
2
DIS@
0.22U_0402_10V6K
PEG_HTX_C_GRX_N14
C520
1
2
DIS@
0.22U_0402_10V6K
PEG_HTX_C_GRX_N13
C529
1
2
DIS@
0.22U_0402_10V6K
PEG_HTX_C_GRX_N12
C534
1
2
DIS@
0.22U_0402_10V6K
PEG_HTX_C_GRX_N11
C538
1
PEG_HTX_C_GRX_N10
2
DIS@
0.22U_0402_10V6K
PEG_HTX_C_GRX_N9
C540
1
2
DIS@
0.22U_0402_10V6K
C542
1
PEG_HTX_C_GRX_N8
2
DIS@
0.22U_0402_10V6K
C544
1
2
DIS@
0.22U_0402_10V6K
PEG_HTX_C_GRX_N7
C546
1
2
DIS@
0.22U_0402_10V6K
PEG_HTX_C_GRX_N6
C548
1
2
DIS@
0.22U_0402_10V6K
PEG_HTX_C_GRX_N5
C550
1
2
DIS@
0.22U_0402_10V6K
PEG_HTX_C_GRX_N4
C552
1
2
DIS@
0.22U_0402_10V6K
PEG_HTX_C_GRX_N3
PEG_HTX_C_GRX_N2
C554
1
2
DIS@
0.22U_0402_10V6K
PEG_HTX_C_GRX_N1
C556
C558
1
1
2
2
DIS@
0.22U_0402_10V6K
DIS@
0.22U_0402_10V6K
PEG_HTX_C_GRX_N0
C560
1
2
DIS@
0.22U_0402_10V6K
PEG_HTX_C_GRX_P15
2
DIS@
0.22U_0402_10V6K
PEG_HTX_C_GRX_P14
PEG_HTX_C_GRX_P13
2
DIS@
0.22U_0402_10V6K
2
DIS@
0.22U_0402_10V6K
PEG_HTX_C_GRX_P12
C536
1
DIS@
0.22U_0402_10V6K
2
DIS@
0.22U_0402_10V6K
PEG_HTX_C_GRX_P11
C539
1
2
PEG_HTX_C_GRX_P10
PEG_HTX_C_GRX_P9
C541
1
2
DIS@
0.22U_0402_10V6K
PEG_HTX_C_GRX_P8
C543
1
2
DIS@
0.22U_0402_10V6K
C545
DIS@
0.22U_0402_10V6K
C547
1
1
DIS@
0.22U_0402_10V6K
PEG_HTX_C_GRX_P7
2
2
PEG_HTX_C_GRX_P6
PEG_HTX_C_GRX_P5
C549
1
2
DIS@
0.22U_0402_10V6K
PEG_HTX_C_GRX_P4
C553
1
1
2
DIS@
0.22U_0402_10V6K
C551
2
DIS@
0.22U_0402_10V6K
PEG_HTX_C_GRX_P3
PEG_HTX_C_GRX_P2
C555
1
2
DIS@
0.22U_0402_10V6K
PEG_HTX_C_GRX_P1
C557
1
2
DIS@
0.22U_0402_10V6K
PEG_HTX_C_GRX_P0
C559
1
2
DIS@
0.22U_0402_10V6K
C561
1
2
DIS@
0.22U_0402_10V6K
PEG_GTX_HRX_N[0..15] 22
PEG_GTX_HRX_P[0..15] 22
PEG_HTX_C_GRX_N[0..15] 22
PEG_HTX_C_GRX_P[0..15] 22
C
1
C515
1
C528
C533
1
1
B
Typ- suggest 220nF. The change in AC capacitor
value from 100nF to 220nF is to enable
compatibility with future platforms having PCIE
Gen3 (8GT/s)
A
A
Security Classification
Issued Date
Compal Secret Data
2010/08/11
Deciphered Date
2011/08/11
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
PROCESSOR(1/7) DMI,FDI,PEG
Size
Document Number
Custom
Date:
P5WE0 M/B LA-6901P Schematic
Friday, August 27, 2010
Sheet
1
Rev
0.1
4
of
59
4
3
2
5
4
3
2
1
+1.05VS_VTT
+1.05VS_VTT
+1.05VS_VTT
XDP_PREQ#
XDP_PRDY#
@
JXDP1
Place near JXDP1
1
1
XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
2
+3VS
D
@
2
@
2
R58
4.7K_0402_5%
1
2
1
SMB_DATA_S3
+3VS
XDP_BPM#4
XDP_BPM#5
14,37 PCH_SMBDATA
6
Q6A
DMN66D0LDW-7_SOT363-6
@
+3VS
XDP_BPM#6
XDP_BPM#7
5
R59
4.7K_0402_5%
1
2
H_CPUPWRGD
+3VS
15,39 PBTN_OUT#
R54
R55
R56
R57
1
1
1
1
@
@
@
@
2
1K_0402_5%
2
0_0402_5%
2
1K_0402_5%
2
0_0402_5%
H_CPUPWRGD_XDP
CFD_PWRBTN#_XDP
XDP_HOOK2
SYS_PWROK_XDP
14,37 PCH_SMBCLK
3
4
SMB_CLK_S3
7
CFG0
CFG0
SYS_PWROK
Q6B
DMN66D0LDW-7_SOT363-6
@
SMB_DATA_S3
SMB_CLK_S3
XDP_TCK
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
C
SNB_IVB# had changed the name to
PROC_SELCT#,function for future platform,
connect to the DF_TVS strap on the PCH
17 H_SNB_IVB#
JCPU1B
p.
su
/x
/
GND1
OBSFN_C0
OBSFN_C1
GND3
OBSDATA_C0
OBSDATA_C1
GND5
OBSDATA_C2
OBSDATA_C3
GND7
OBSFN_D0
OBSFN_D1
GND9
OBSDATA_D0
OBSDATA_D1
GND11
OBSDATA_D2
OBSDATA_D3
GND13
ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
GND15
TD0
TRST#
TDI
TMS
GND17
SAMTE_BSH-030-01-L-D-A
GND0
OBSFN_A0
OBSFN_A1
GND2
OBSDATA_A0
OBSDATA_A1
GND4
OBSDATA_A2
OBSDATA_A3
GND6
OBSFN_B0
OBSFN_B1
GND8
OBSDATA_B0
OBSDATA_B1
GND10
OBSDATA_B2
OBSDATA_B3
GND12
PWRGOOD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
GND14
SDA
SCL
TCK1
TCK0
GND16
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
C128
C128
0.1U_0402_16V4Z
MISC
C26
AN34
SNB_IVB#
SKTOCC#
CLOCKS
T6
PAD
@
R93
0_0402_5%
1
2
H_CATERR#
AL33
Processor Pullups
R84
18,39
H_PECI
H_PECI_ISO
yc
om
THERMAL
C59
0.1U_0402_16V4Z
0.1U_0402_16V4Z
D
+3VS
XDP_DBRESET#
R40
2
1
1K_0402_5%
CLK_CPU_ITP
CLK_CPU_ITP#
XDP_RST#_R
R39
XDP_DBRESET#
CLK_CPU_ITP 14
CLK_CPU_ITP# 14
2
@
1
1K_0402_5%
PLT_RST# 17,35,38,39,45
XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS
C
BCLK
BCLK#
A28
A27
CLK_CPU_DMI
CLK_CPU_DMI#
CLK_CPU_DMI 14
CLK_CPU_DMI# 14
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
A16
A15
R516
2
R518
2
1
1K_0402_5%
1
1K_0402_5%
+1.05VS_VTT
If use External Graphic or
use integrated without eDP
DPLL_REF_SSCLK PD 1K_5% to GND
DPLL_REF_SSCLK# PH 1K_5% to +1.05VS_VTT
CATERR#
AN33
PECI
SM_DRAMRST#
R8
SM_DRAMRST#
SM_DRAMRST# 6
2
+1.05VS_VTT
39,49 H_PROCHOT#
2
R91
1
62_0402_5%
H_PROCHOT#
R92
56_0402_5%
H_PROCHOT#_R
1
2
R97
0_0402_5%
H_THEMTRIP#_R
1
2
DDR3
MISC
H_CPUPWRGD_R
1
10K_0402_5%
AL32
PROCHOT#
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
AK1
A5
A4
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
R231
2
1
140_0402_1%
R566
2
R571
2
1
25.5_0402_1%
1
200_0402_1%
18 H_THRMTRIP#
AN32
:/
/m
THERMTRIP#
DDR3 Compensation Signals
PU/PD for JTAG signals
XDP_PRDY#_R
AP29
XDP_PREQ#_R
AP27
XDP_TCK
AR26
XDP_TMS
AR27
XDP_TRST#
AP30
XDP_TDI_R
AR28
XDP_TDO_R
AP26
Buffered reset to CPU
+3VS
+1.05VS_VTT
PRDY#
PREQ#
PWR MANAGEMENT
1
B
+1.05VS_VTT
0_0402_5%
@
R80
1
2
@
R83
1
2
0_0402_5%
XDP_TMS
XDP_PRDY#
XDP_PREQ#
R106
2
1
51_0402_5%
XDP_TDI_R
XDP_TDO
R99
2
1
51_0402_5%
JTAG & BPM
C162
0.1U_0402_16V4Z
15 H_PM_SYNC
R96
0_0402_5%
1
2
H_PM_SYNC_R
AM34
2
1
PM_SYNC
TCK
TMS
TRST#
ESD request...2010/07/27
XDP_TDI
2
0_0402_5%
XDP_TDO
2
0_0402_5%
R105
XDP_TCK
2
1
51_0402_5%
B
XDP_TRST#
R111
2
1
51_0402_5%
tt
p
R90
75_0402_5%
1
PLT_RST#
18 H_CPUPWRGD
@
R782
2
0_0402_5%
1
R81
0_0402_5%
H_CPUPWRGD_R
1
2
AP33
TDI
TDO
1
R100
1
R110
R95
2
1
51_0402_5%
5
2
U7
P
BUFO_CPU_RST#
NC
A
G
1
R64
2
2
0_0402_5%
1
Y
3
4
R87
43_0402_1%
BUF_CPU_RST#
1
2
@
R88
0_0402_1%
UNCOREPWRGOOD
UNCOREPWRGOOD: CORE
OK
PM_DRAM_PWRGD_R
V8
DBR#
AL35
DBRESET#_R
XDP_DBRESET#
1
R101
XDP_BPM#0_R
XDP_BPM#1_R
XDP_BPM#2_R
XDP_BPM#3_R
XDP_BPM#4_R
XDP_BPM#5_R
XDP_BPM#6_R
XDP_BPM#7_R
2
0_0402_5%
XDP_DBRESET# 15
SM_DRAMPWROK
SN74LVC1G07DCKR_SC70-5
SM_DRAMPWROK:DRAM power ok
BUF_CPU_RST#
RESET#:
ok
CPU
reset
2
AR33
RESET#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32
0_0402_5%
2
@
1
R79
h
0_0402_5%
2
@
1
R75
0_0402_5%
0_0402_5%
2
2
@
@
1
1
R73
R66
0_0402_5%
0_0402_5%
2
2
@
@
1
1
R62
R51
0_0402_5%
R52
0_0402_5%
2
2
@
@
1
1
R53
XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_BPM#6
XDP_BPM#7
+3VALW
+1.5V_CPU_VDDQ
ESD request...2010/07/27
Sandy Bridge_rPGA_Rev0p61
CONN@
C307
0.1U_0402_16V4Z
1
1
R205
2
A
15 SYS_PWROK
15 PM_DRAM_PWRGD
U11
74AHC1G09GW_TSSOP5
PM_SYS_PWRGD_BUF
200_0402_5%
2
A
5
PM_DRAM_PWRGD_R
1
2
B
A
O
G
3
4
1
R204
2
0_0402_1%
P
1
R203
39_0402_1%
Security Classification
Issued Date
Compal Secret Data
2010/08/11
Deciphered Date
2
@
2011/08/11
Title
Compal Electronics, Inc.
PROCESSOR(2/7) PM,XDP,CLK
P5WE0 M/B LA-6901P Schematic
Friday, August 27, 2010
1
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
Size Document Number
Custom
Date:
Rev
0.1
4
3
2
Sheet
5
of
59

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