CS5331.PDF

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CS5330A
CS5331A
8-Pin, Stereo A/D Converter for Digital Audio
Features
General Description
The CS5330A / 31A is a complete stereo analog-to-
digital converter which performs anti-alias filtering,
sampling and analog-to-digital conversion generating
18-bit values for both left and right inputs in serial form.
The output sample rate can be infinitely adjusted be-
tween 2 and 50 kHz.
The CS5330A / 31A operates from a single +5V supply
and requires only 150 mW for normal operation, mak-
ing it ideal for battery-powered applications.
The ADC uses delta-sigma modulation with 128X over-
sampling, followed by digital filtering and decimation,
which removes the need for an external anti-alias filter.
The linear-phase digital filter has a passband to
21.7 kHz, 0.05 dB passband ripple and >80 dB stop-
band rejection. The device also contains a high pass
filter to remove DC offsets.
The device is available in a 0.208" wide, 8-pin surface
mount package.
ORDERING INFORMATION:
Model
Temp. Range
CS5330A-KS -10° to 70°C
CS5331A-KS -10° to 70°C
CS5330A-BS -40° to +85°C
CS5331A-BS -40° to +85°C
MCLK
4
Voltage Reference
Serial Output Interface
8
LP Filter
S/H
DAC
Digital Decimation
Filter
Comparator
DAC
7
VA+
High
Pass
Filter
Digital Decimation
Filter
Comparator
SCLK
2
LRCK
3
1
SDATA
•
•
•
•
•
•
•
Single +5 V Power Supply
18-Bit Resolution
94 dB Dynamic Range
Linear Phase Digital Anti-Alias Filtering
0.05dB Passband Ripple
80dB Stopband Rejection
Low Power Dissipation: 150 mW
Power-Down Mode for Portable
Applications
Complete CMOS Stereo A/D System
Delta-Sigma A/D Converters
Digital Anti-Alias Filtering
S/H Circuitry and Voltage Reference
Adjustable System Sampling Rates
including 32kHz, 44.1 kHz & 48kHz
Package Type
8-pin plastic SOIC
8-pin plastic SOIC
8-pin plastic SOIC
8-pin plastic SOIC
AINL
High
Pass
Filter
AINR
5
S/H
LP Filter
AGND
6
Cirrus Logic, Inc.
Crystal Semiconductor Product Division
P.O. Box 17847, Austin, TX 78760
(512) 445-7222 FAX: (512) 445-7581
http://www.crystal.com
Copyright
©
Cirrus Logic, Inc. 1999
(All Rights Reserved)
MAR ’99
DS138F2
1
CS5330A/CS5331A
ANALOG CHARACTERISTICS
(T
A
= 25°C; VA+ = 5V; -1 dBFS Input Sinewave, 997 Hz;
Fs = 48 kHz; MCLK = 12.288 MHz; SCLK = 3.072 MHz; Measurement Bandwidth is 10 Hz to 20 kHz unless oth-
erwise specified; Logic 0 = 0V, Logic 1 = VD+)
Parameter
Temperature Range
5330A/31A-KS
Symbol Min
Typ
Max
T
A
A-weighted
(Note 1)
-1dB
-20dB
-60dB
-1dB
(dc to 20 kHz)
THD+N
-
-
-
THD
-
-
-
-
-
-
(Note 2)
VIN
ZIN
-
3.6
-
-
(Note 3)
VA+
Power down
Power Dissipation
(Note 3)
Normal
Power Down
IA+
-
-
-
-
30
100
150
0.5
42
1000
220
5.25
-
-
-
-
-
-
30
100
150
0.5
50
42
1000
220
5.25
-
mA
µA
mW
mW
dB
-84
-72
-32
0.003
0
90
0.1
-
150
-
4.0
100
2.4
75
66
26
0.02
-
-
-
±10
-
0
4.4
-
-
-
-
-
-
-
-
-
-
-
-
3.6
-
-
-84
-72
-32
0.003
0
90
0.1
-
150
-
4.0
100
2.4
75
66
26
0.02
-
-
-
±10
-
0
4.4
-
-
dB
dB
dB
%
Degree
dB
dB
%
ppm/°C
LSB
Vpp
kΩ
V
88
86
-10 to +70
94
92
-
-
86
84
5330A/31A-BS
Min
Typ
Max
-40 to +85
94
92
-
-
Units
°C
dB
dB
Dynamic Performance
Dynamic Range
Total Harmonic Distortion+Noise
Total Harmonic Distortion
Interchannel Phase Deviation
Interchannel Isolation
dc Accuracy
Interchannel Gain Mismatch
Gain Error
Gain Drift
Offset Error
Analog Input
Full Scale Input Voltage Range
Input Impedance
Input Bias Voltage
(Fs = 48 kHz)
Power Supplies
Power Supply Current
Power Supply Rejection Ratio
PSRR
-
50
* Refer to Parameter Definitions at the end of this data sheet.
Notes: 1. Referenced to typical full-scale input voltage (4.0 Vpp)
2. Internal highpass filter removes offset.
3. For max power calculations, VD = 5.25 V.
2
DS138F2
CS5330A/CS5331A
DIGITAL CHARACTERISTICS
(T
A
= 25
°C;
VA+ = 5V
±
5%)
Parameter
High-Level Input Voltage
Low-Level Input Voltage
High-Level Output Voltage at lo = -20
µA
Low-Level Output Voltage at lo = 20
µA
Input Leakage Current
Symbol
V
IH
V
IL
V
OH
V
OL
I
in
Min
2.4
-
(VD+)-1.0
-
-
Typ
-
-
-
-
-
Max
-
0.8
-
0.4
±10.0
Units
V
V
V
V
µA
DIGITAL FILTER CHARACTERISTICS
(T
A
= 25
°C;
VA+ = 5V
±
5%; Fs = 48 kHz)
Parameter
Passband
Passband Ripple
Stopband
Stopband Attenuation
Group Delay
Group Delay Variation vs. Frequency
(Note 4)
(Note 5)
(Note 6)
t
gd
∆t
gd
(Note 4)
(Note 4)
(0.05 dB)
(Note 4)
Symbol
Min
0.02
-
29
80
-
-
-
-
-
Typ
-
-
-
-
15/Fs
-
3.7
20
10
Max
21.7
±0.05
6115
-
-
0
-
-
-
Units
kHz
dB
kHz
dB
s
µs
Hz
Hz
Degree
High Pass Filter Characteristics
Frequency Response:
Phase Deviation
-3 dB
-0.1 dB
@ 20 Hz
Passband Ripple
-
-
0
dB
Notes: 4. Filter characteristics scale with output sample rate.
5. The analog modulator samples the input at 6.144 MHz for an output sample rate of 48 kHz. There is
no rejection of input signals which are multiples of the sampling frequency ( n x 6.144 MHz
±21.7kHz
where n = 0,1,2,3...).
6. Group delay for Fs = 48kHz, t
gd
= 15/48kHz = 312µs
DS138F2
3
CS5330A/CS5331A
ABSOLUTE MAXIMUM RATINGS
(AGND = 0V, all voltages with respect to ground.)
Parameter
DC Power Supply:
Input Current, Any Pin Except Supplies
Analog Input Voltage
Digital Input Voltage
Ambient Temperature (power applied)
Storage Temperature
(Note 7)
(Note 8)
(Note 8)
Symbol
VA+
Iin
V
INA
V
IND
T
A
T
stg
Min
-0.3
-
-0.7
-0.7
-55
-65
Typ
-
-
-
-
-
-
Max
+6.0
±10
(VA+)+0.7
(VA+)+0.7
+125
+150
Units
V
mA
V
V
°C
°C
Notes: 7. Any Pin except supplies. Transient currents of up to +/- 100 mA on the analog input pins will not
cause SCR latch-up.
8. The maximum over/under voltage is limited by the input current.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AGND = 0V; all voltages with respect to ground)
Parameter
DC Power Supplies:
Analog Input Voltage
(Note 9)
Symbol
VA+
V
IN
Min
4.75
-
Typ
5.0
4
Max
5.25
-
2.6
Units
V
Vpp
V
Analog Input Bias Voltage
2.2
2.4
Note: 9. The output codes will clip at full scale with input signals > Full Scale and < VA+.
Specifications are subject to change without notice.
4
DS138F2
CS5330A/CS5331A
SWITCHING CHARACTERISTICS
Parameter
Output Sample Rate
MCLK Period
MCLK Low
MCLK High
MCLK Period
MCLK Low
MCLK High
MCLK Period
MCLK Low
MCLK High
MASTER MODE
SCLK falling to LRCK
SCLK falling to SDATA valid
SCLK Duty cycle
SLAVE MODE
LRCK duty cycle
SCLK Period
SCLK Pulse Width Low
SCLK Pulse Width High
SCLK falling to SDATA valid
LRCK edge to MSB valid
SCLK rising to LRCK edge delay
LRCK edge to rising SCLK setup time
1
1
Notes: 10.
11.
−15
ns
64 F
s
128 F
s
(T
A
= 25
°C;
VA+ = 5V
±
5%; Inputs: Logic 0 = 0V, Logic
1 = VA+; C
L
= 20 pF) Switching characteristics are guaranteed by characterization.
Symbol
Fs
MCLK / LRCK = 256
MCLK / LRCK = 256
MCLK / LRCK = 256
MCLK / LRCK = 384
MCLK / LRCK = 384
MCLK / LRCK = 384
MCLK / LRCK = 512
MCLK / LRCK = 512
MCLK / LRCK = 512
t clkw
t clkl
t clkh
t clkw
t clkl
t clkh
t clkw
t clkl
t clkh
t mslr
t sdo
Min
2
78
31
31
52
20
20
39
13
13
-10
-10
-
25
t sclkw
t sclkl
t sclkh
t dss
t lrdss
t slr1
t slr2
12.
(Note 10)
(Note 11)
20
-
-
20
(Note 12)
-
-
-
-
50
50
-
-
-
-
-
-
-
-
-
-
-
Typ
-
Max
50
1000
1000
1000
1000
1000
1000
1000
1000
1000
10
35
-
75
-
-
-
(Note 12)
(Note 12)
-
-
Units
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
%
ns
ns
ns
ns
ns
ns
ns
1
+
5 ns
256 F
s
DS138F2
5

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