parm_Athena(5).txt

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//****************** Copyright 2003 Broadcom Corp. *********************

//

// Description:	Zeus on Aston Martin

//

// $File: //depot/Sources/Common/sysparm/.txt $

// $Revision: $

// $Changelist: $

//

//******************************************************************************

#include "parm_dsp.txt"

#include "stack/parm_stack.txt"

//*****************************************************************************

// Spinner/WCDMA setting

//*****************************************************************************

#include "UmtsFw/parm_UmtsFw.txt"

#include "log/parm_log.txt"



SYSPARM_FILE_VERSION			0x0002



MANUFACTURER_NAME			Broadcom

MODEL_NAME				Wedge

MSTYPE					MODEM





IMEI_TAC				000000		// Type Approval Code

IMEI_FAC				00		// Final Assembly Code

IMEI_SNR				009876		// Serial Number



// Second IMEI for dual-SIM feature

IMEI_TAC_2				000000		// Type Approval Code

IMEI_FAC_2				00			// Final Assembly Code

IMEI_SNR_2				000000		// Serial Number



CLASS_UMTS				2			// FIXME - ONLY INTRODUCED TO REMOVE ERRORS

								// 0 - GSM only

								// 1 - UMTS dual-mode, default GSM

								// 2 - UMTS dual-mode, default UMTS

								// 3 - UMTS only

								

// ** AVS parameters **



AVS				DISABLE		// AVS: Enable/Disable at initialization.



// AVS: Refer to voltage values mapping above. 

// 	If 0 or keyword is not specified in sysparm 	then set to default by PMU sysparms 

// 	If >0 and AVS detects silicon is FF or TT, then it will use lower voltage specified here 

#if defined(FEATURE_APPS_832Mhz) 

FF_BIN_VOLTAGE			0x0A		

#elif defined(FEATURE_APPS_728Mhz) 

FF_BIN_VOLTAGE			0x0B 

#else 

FF_BIN_VOLTAGE			0x0A		// Default value is set at 832MHz FFTT voltage 

#endif



// ** DVFS parameters **

DYNAMIC_ENERGY_MANAGEMENT 	ENABLE		// DVFS Enable/Disable at initialization.

NON_TURBO_VOLTAGE		0x0C		// DVFS: Refer to voltage values mapping above. 

						//  	VCore out for non-turbo frequency during DVFS scale-down.

						// 	Turbo mode is set by PMU sysparms for NM1 and NM2 in associated CSR registers.





#if defined(_BCM2091_)

  DEEP_SLEEP		ENABLE

  DORMANT_MODE		DISABLE

  PEDESTAL_MODE		ENABLE

#else

  DEEP_SLEEP		ENABLE

  DORMANT_MODE		DISABLE

  PEDESTAL_MODE		ENABLE

#endif



//*************************************************************************

// DEBUG_lA			control logic analyzer test point

// LA_RTOS			0x00000001

// LA_PHY			0x00000002

// LA_MP			0x00000004

// LA_DATA			0x00000008

// LA_ECDC			0x00000010

// LA_STACK			0x00000020

// LA_GENERAL		0x00000080

//*************************************************************************

DEBUG_LA		0x00000000



//***************************************************************************

//	AMR SNR BIAS CORRECTION TABLE

//***************************************************************************

AMR_SNR_BIAS		0	48	 103   163	 215   257	 300   450

AMR_SNR_CAL_POINT -200	-20	  80   160	 240   320	 400   660





//	SIM Profile: these settings reflect the STK feature support status of the

//				 BRCM platform.	 The data is sent in the Terminal Profile

//				 command to SIM/USIM during powerup.

//

//				 The data needs to be updated based on the support

//				 of MMI and host for each individual project. See Section 5.2

//				 of ETSI TS 101 267 (GSM 11.14) for the bit settings.

//

//				 For example, extension text feature requires the display of

//				 240 or more characters on the screen. It is supported by BRCM

//				 platform, but may not be supported by MMI which can not

//				 display such a long text string on the screen.

//

//----------------------------------------------------------------------------

SIM_PROFILE	0xff 0xff 0xff 0xff 0x7f 0x1f 0x00 0xff 0xff 0x03 0x05 0x1f 0x22 0x04 0x0b 0x00 0x03





//SD Slot number to be used

FFS_SD_SLOT_NUM  2



//******************************************************************************

//	 Test and Tracing Control

//******************************************************************************

DEBUG_VALUE0	0			// Non-Zero forces DAI mode

DEBUG_VALUE1	0			// Non-Zero overrides speaker gain





//*****************************************************************************

// MULIT_RATE UART support			ML2022

// UART_TYPE	UARTA_TYPE(high byte) + UARTB_TYPE(low	byte)

//		UARTA for AT command	UARTB for logging

//

// default setting should be 0x0606(115.2k for both ports)

// other choice:	0x060a (AT command 115.2k, logging 921.6k)

//			0x0609 (AT command 115.2k, logging 460.8k)

// MSB of each bytes indicating auto flow-control on(1)/off(0)

// e.g. auto flow-control ON for UART A at 921k : 0x8Axx 

//

//	0	_2dot4,		// 2400

//	1	_4dot8,		// 4800

//	2	_9dot6,		// 9600

//	3	_19dot2,	// 19200

//	4	_38dot4,	// 38400

//	5	_57dot6,	// 57600

//	6	_115dot2,	// 115200

//	7	_128dot0,	// 128000

//	8	_230dot4,	// 230400

//	9	_460dot8,	// 460800

//	10	_921dot6	// 921600

//*****************************************************************************

UART_TYPE		0x060a

UART_TYPE2      0x0a06      //For UART C & D

DEFAULT_AT_DEVICE	A		// A - UARTA, B - UARTB, C - UARTC, U - USB, N - NULL

DEFAULT_LOG_PORT	B		// A - UARTA, B - UARTB, C - UARTC, U - USB, N - NULL



WDT_TIMEOUT		0		// hardware watchdog timer in seconds (zero to disable watchdog)

JTAG_DEBUG		DISABLE		// DISABLE - normal operation, ENABLE - JTAG debug operation





#if defined(_BCM2091_) 

ANTENNA_SWITCH_MASK	0x10F		// This is for Single-Antenna solution, the mask should match with the GPEN setting for antenna switchplexer

ANTENNA_SWITCH_VAL	0x108		// Default value for 3G: GPEN2-0 = 000

#else

ANTENNA_SWITCH_MASK	0x087		// This is for Single-Antenna solution, the mask should match with the GPEN setting for antenna switchplexer

ANTENNA_SWITCH_VAL	0x005		// Default value for 3G: GPEN2-0 = 000

#endif



//******************************************************************************

// WCDMA OLPC parameters

//*******************************************************************************

MIN_TARGETSIR_UNGUIDED	-92274688   	// 92274688  //OLPC minimum target SIR for unguided trch case. it is scaled up by 2^24

					// BLER is x times more than the target, and x > SCALED_NONREF_BLER_THD/32, then the non-ref. trch becomes active



					// and max_min > zero_min*VITERBI_VALID_BLOCK_MULTIPLY_THD then an empty block is considered as error



//OLPC_RESET_MARGIN		  1     //1dB	 This is for OLPC out-of-lock condition counter. If target SIR is less than measured SIR plus OLPC_RESET_MARGIN, reset the counter

					// For example: OLPC_BLER_SCALE =8, MAX_COUNTER = 25;	OLPC_BLER_SCALE =16, MAX_COUNTER = 50



//*****************************************************************************

// Hardware Configuration

//*****************************************************************************

IOCR_VAL			0x0084	//0x008160ce

CCR				0xf1ff

PCR_VAL				0x8033	//ML2022 default 0x33



#if defined(_BCM2091_) 

IOCR2_VAL        		0x44400000

IOCR7_VAL        		0x0555a200

#endif



FLASH_PAGE_MODE			2	// =0: disable page mode; =1: enable page mode;	 =2: enable burst mode

SRAM_PAGE_MODE			0	// =0: disable page mode; =1: enable page mode;	 =2: enable burst mode



//******************************************************************************

// Multislot Tx Power Cutback (Starting from 1 slot)

//*******************************************************************************

//TXPWR_CUTBACK   0   3   4   6           // 10log(num_tx_slots)



//***************************************************************************

//	PRODUCTION TEST MODE (U)ARFCN TABLES (8 ENTRIES/BAND)

//***************************************************************************



//UMTS TEST FREQ

//TEST_FREQ_UMTS_BAND_VI     0      0      0    0      0      0      0      0

//TEST_FREQ_UMTS_BAND_VII    0      0      0    0      0      0      0      0

//TEST_FREQ_UMTS_BAND_VIII   0      0      0    0      0      0      0      0

//TEST_FREQ_UMTS_BAND_IX     0      0      0    0      0      0      0      0







#if defined(_NXP_) 

//******************************************************************************

// Set up one-time programming for BB ASIC

//******************************************************************************

//			Address Value		// Comments

//			======= ======		== ========

WRITE INITONLY		0xe540  0x0020		// AMCR (Audio Module Control Register) -- Enabled VBEN

DELAY INITONLY		0x7fff			// need extra delay for ML2022 DSP

WRITE INITONLY		0xe540  0x0000		// AMCR -- Disable VBEN

DELAY INITONLY		0x7fff



#endif 



#if defined(_NXP_) 

#include "rfic/init_si4228.txt"

#else // BCM2091

	#include "rfic/init_2091.txt"

#if defined(_BCM2091_) && (RF_CHIP_REVISION == 11)  //bCM2091 A1

	#include "rfic/init_2091_3G.txt"

#endif

#if defined(_BCM2091_) && (RF_CHIP_REVISION == 20)  //bCM2091 B0

#include "rfic/init_2091_3GB0.txt"

#endif

#endif //#if defined(_NXP_) 



#if defined(_BCM2091_)

UmtsPS_INIT_OFF    1   //This is for UmtsPS to determine initialization from : 1: rfic/init_2091_3G.txt; else: umts ps fw. 

#endif 



#if defined(_NXP_) 





//	Set up programming for BB ASIC.



//			Address Value		// Comments

//			======= ======	        == ========

WRITE ANYBAND 		0xe546  0x0002		// AMPCR

WRITE ANYBAND 		0xe5c0  0x0000		// RCOR

WRITE ANYBAND		0xe5c1	0x0000	    	// RCDR

WRITE ANYBAND 		0xe501  0x1387		// CHAR (Counter Hold A Register)

WRITE ANYBAND 		0xe502  0x1387		// CHBR (Counter Hold B Register)

WRITE ANYBAND 		0xe573  0x8000		// FRQO...
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