emif.pdf

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®
EMIF10-1K010F1
A.S.D.
TM
EMI FILTER
INCLUDING ESD PROTECTION
MAIN APPLICATIONS
Where EMI filtering in ESD sensitive equipment is
required:
Computers and printers
Communication systems
Mobile phones
MCU Boards
s
s
s
s
DESCRIPTION
The EMIF10-1K010F1 is a highly integrated
device designed to suppress EMI / RFI noise in all
systems
subjected
to
electromagnetic
interferences. The EMIF10 flip-chip packaging
means the package size is equal to the die size.
That's why EMIF10-1K010F1 is a very small
device.
Additionally, this filter includes an ESD protection
circuitry which prevents the protected device from
destruction when subjected to ESD surges up to
15 kV.
BENEFITS
s
s
s
s
s
Flip Chip package
s
s
EMI symetrical (I/O) low-pass filter
High efficiency in EMI filtering
Very low PCB space consuming: 2.6 x 2.6 mm
2
Very thin package: 0.65 mm
High efficiency in ESD suppression on both input
& output PINS (IEC61000-4-2 level 4).
High reliability offered by monolithic integration
High reducing of parasitic elements through in-
tegration & wafer level packaging.
PIN CONFIGURATION (Ball Side)
A
1
2
3
I3
B
I1
I5
C
I2
I4
I6
I8
I10
D
O1
O3
O5
O7
O9
E
O2
O4
O6
O8
O10
BASIC CELL CONFIGURATION
Low-pass filter
GND GND
GND GND
I7
I9
Input
Output
4
5
Ri/o = 1k
Ω
Cinput = 100pF
TM
: ASD is a trademark of STMicroelectronics.
July 2002 - Ed: 3C
1/13
EMIF10-1K010F1
COMPLIES WITH FOLLOWING STANDARD:
IEC61000-4-2 level 4 15 KV
(air discharge)
8 kV
(contact discharge)
on input & output pins
MIL STD 883C - Method 3015-6 Class 3
Filtering Behavior
S21 (dB)
0
-10
-20
-30
ESD response to IEC61000-4-2 (16kV Air Dis-
charge)
V(in1)
V(out1)
-40
-50
1
10
100
frequency (MHz)
1,000
Capacitance versus reverse applied voltage.
C(pF)
100
90
80
70
60
50
40
30
20
10
0
F=1MHz
Vosc=30mV
VR(V)
1
2
5
10
2/13
EMIF10-1K010F1
ABSOLUTE MAXIMUM RATINGS
(T
amb
= 25 °C)
Symbol
V
PP
Parameter and test conditions
ESD discharge IEC61000-4-2, air discharge
ESD discharge IEC61000-4-2, contact discharge
MIL STD 883C Method 3015-6
Junction temperature
Operating temperature range
Storage temperature range
Value
15
8
25
125
-40 to + 85
-55 to +150
Unit
kV
T
j
T
op
T
stg
°C
°C
°C
ELECTRICAL CHARACTERISTICS
(T
amb
= 25°C)
Symbol
V
BR
I
RM
V
RM
V
CL
R
d
I
PP
R
I/O
C
in
Parameters
Breakdown voltage
Leakage current @ V
RM
Stand-off voltage
Clamping voltage
Dynamic impedance
Peak pulse current
Series resistance between Input &
Output
Input capacitance per line
slope : 1 / R
d
I
PP
V
CL
V
BR
V
RM
I
RM
I
R
I
V
Symbol
V
BR
I
RM
R
d
R
I/O
Cline
At 0V bias
I
R
= 1mA
Test conditions
Min
6
Typ
8
Max
10
500
Unit
V
nA
Ω
V
RM
= 3V per line
I
PP
= 10A, t
p
= 2.5µs (see note 1)
900
80
1
1000
100
1100
120
Ω
pF
Note 1:
To calculate the ESD residual voltage, please refer to the paragraph "ESD PROTECTION" on page 5.
3/13
EMIF10-1K010F1
TECHNICAL INFORMATION
FREQUENCY BEHAVIOR
The EMIF10-1K010F1 is firstly designed as an
EMI / RFI filter. This low-pass filter is characterized
by the following parameters:
- Cut-off frequency
- Insertion loss
- High frequency
Fig. A1:
Frequency response curve
S21 (dB)
0
-10
-20
Figure A1 gives these parameters, in particular the
signal rejection at the GSM frequency:
- 25dB @ 900Mhz
- 14dB @ 1800Mhz
-30
-40
-50
1
10
100
frequency (MHz)
1,000
Fig. A2:
Measurements conditions
TEST BOARD
50
Ω
in1
EMIF10
1K010F1
out1
50
Ω
Vg
4/13
EMIF10-1K010F1
ESD PROTECTION
In addition with the filtering the EMIF10-1K010F1 is particularly optimized to perform ESD protection.
ESD protection is based on the use of device which clamps at:
V
cl
=
V
br
+
R
d
⋅
I
pp
This protection function is splitted in 2 stages. As shown in Figure A3, the ESD strikes are clamped by
the first stage S1 and then its remaining overvoltage is applied to the second stage through the resis-
tor R. Such a configuration makes the output voltage very low at the Vout level.
Fig. A3:
ESD clamping behavior
Rg
S1
R=1k
S2
Rd
Rd
Vg
Vbr
Vinput
Voutput
Vbr
Rload
Device
to be
protected
ESD Surge
EMIF10-1k010F1
To have a good approximation of the remaining voltages at both Vin and Vout stages, we give the typical
dynamic resistance value Rd. By taking into account these following hypothesis : R>>Rd, Rg>>Rd and
Rload>>Rd, it gives these formulas:
R
g
⋅
V
br
+
R
d
⋅
V
g
R
g
R
⋅
V
br
+
R
d
⋅
V
in
Voutput
=
R
Vinpout
=
The results of the calculation done for an IEC 1000-4-2 Level 4 Contact Discharge surge (Vg=8kV,
Rg=330Ω ) and Vbr=7V (typ.) give:
Vinput = 31.24V
Voutput = 7.03V
This confirms the very low remaining voltage across the device to be protected. It is also important to note
that in this approximation the parasitic inductance effect was not taken into account. This could be few
tenths of volts during few ns at the Vin side. This parasitic effect is not present at the Vout side due the low
current involved after the series resistance R.
5/13

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