1911.PDF

(276 KB) Pobierz
19-4782; Rev 1; 3/99
NUAL
KIT MA
ATION
ET
EVALU
TA SHE
WS DA
FOLLO
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
Features
o
12-Bit Resolution, 1/2LSB Linearity
o
+5V Single-Supply Operation
o
SPI/QSPI and MICROWIRE-Compatible
3-Wire Interface
o
Four Software-Selectable Input Ranges
MAX1270: 0 to +10V, 0 to +5V, ±10V, ±5V
MAX1271: 0 to V
REF
, 0 to V
REF
/2, ±V
REF
,
±V
REF
/2
o
Eight Analog Input Channels
o
110ksps Sampling Rate
o
±16.5V Overvoltage-Tolerant Input Multiplexer
o
Internal 4.096V or External Reference
o
Two Power-Down Modes
o
Internal or External Clock
o
24-Pin Narrow DIP or 28-Pin SSOP Packages
General Description
The MAX1270/MAX1271 are multirange, 12-bit data-
acquisition systems (DAS) that require only a single +5V
supply for operation, yet accept signals at their analog
inputs that may span above the power-supply rail and
below ground. These systems provide eight analog
input channels that are independently software pro-
grammable for a variety of ranges: ±10V, ±5V, 0 to
+10V, 0 to +5V for the MAX1270; ±V
REF
, ±V
REF
/2, 0 to
V
REF
, 0 to V
REF
/2 for the MAX1271. This range switch-
ing increases the effective dynamic range to 14 bits and
provides the flexibility to interface 4–20mA, ±12V, and
±15V powered sensors directly to a single +5V system.
In addition, these converters are fault protected to
±16.5V; a fault condition on any channel will
not
affect
the conversion result of the selected channel. Other fea-
tures include a 5MHz bandwidth track/hold, software-
selectable internal/external clock, 110ksps throughput
rate, and internal 4.096V or external reference opera-
tion.
The MAX1270/MAX1271 serial interface directly con-
nects to SPI™/QSPI™ and MICROWIRE™ devices with-
out external logic.
A hardware shutdown input (SHDN) and two software-
programmable power-down modes, standby (STBYPD)
or full power-down (FULLPD), are provided for low-cur-
rent shutdown between conversions. In standby mode,
the reference buffer remains active, eliminating start-up
delays.
The MAX1270/MAX1271 are available in 24-pin narrow
DIP or space-saving 28-pin SSOP packages.
MAX1270/MAX1271
Typical Operating Circuit
+5V
0.1µF
V
DD
SHDN
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
Applications
Industrial Control Systems
Data-Acquisition Systems
Robotics
Automatic Testing
Battery-Powered Instruments
Medical Instruments
ANALOG
INPUTS
MAX1270
MAX1271
MC68HCXX
CS
SCLK
DIN
DOUT
SSTRB
AGND
I/O
SCK
MOSI
MISO
REF
REFADJ
4.7µF
0.01µF
DGND
Ordering Information
PART
TEMP.
RANGE
PIN-PACKAGE
INL
(LSB)
±1/2
±1
±1/2
±1
MAX1270ACNG
0°C to +70°C 24 Narrow Plastic DIP
MAX1270BCNG 0°C to +70°C 24 Narrow Plastic DIP
0°C to +70°C 28 SSOP
MAX1270ACAI
MAX1270BCAI
0°C to +70°C 28 SSOP
Ordering Information continued at end of data sheet.
Pin Configurations appear at end of data sheet.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
7-169
____________________________________________________________
Maxim Integrated Products
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
MAX1270/MAX1271
ABSOLUTE MAXIMUM RATINGS
V
DD
to AGND............................................................-0.3V to +6V
AGND to DGND.....................................................-0.3V to +0.3V
CH0–CH7 to AGND ......................................................... ±16.5V
REF, REFADJ to AGND ..............................-0.3V to (V
DD
+ 0.3V)
SSTRB, DOUT to DGND.............................-0.3V to (V
DD
+ 0.3V)
SHDN, CS,
DIN, SCLK to DGND..............................-0.3V to +6V
Max Current into Any Pin ....................................................50mA
Continuous Power Dissipation (T
A
= +70°C)
24-Pin Narrow DIP (derate 13.33mW/°C above +70°C) ..1067mW
28-Pin SSOP (derate 9.52mW/°C above +70°C) ..........762mW
Operating Temperature Ranges
MAX127_C_ _ ......................................................0°C to +70°C
MAX127_E_ _....................................................-40°C to +85°C
Storage Temperature Range ............................-65°C to +150°C
Lead Temperature (soldering, 10sec) ............................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
DD
= +5.0V ±5%; unipolar/bipolar range; external reference mode, V
REF
= +4.096V; 4.7µF at REF; external clock, f
CLK
= 2.0MHz
(50% duty cycle), 18 clock/conversion cycle, 110ksps; T
A
= T
MIN
to T
MAX
; unless otherwise noted. Typical values are T
A
= +25°C.)
PARAMETERS
ACCURACY
(Note 1)
ACCURACY (Note 1)
Resolution
Integral Nonlinearity
Differential Nonlinearity
INL
DNL
MAX127_A
MAX127_B
No missing codes over temperature
Unipolar
Offset Error
Bipolar
Channel-to-Channel Offset
Error Matching
Unipolar
Bipolar
Unipolar
Gain Error
(Note 2)
Bipolar
Gain Error Temperature
Coefficient (Note 2)
MAX127_A
MAX127_B
MAX127_A
MAX127_B
±3
±5
MAX127_A
MAX127_B
MAX127_A
MAX127_B
±0.1
±0.3
±7
±10
±7
±10
ppm/°C
LSB
12
±0.5
±1.0
±1
±3
±5
±5
±10
LSB
LSB
bits
LSB
LSB
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Unipolar, external reference
Bipolar, external reference
DYNAMIC
SPECIFICATIONS (10kHz sine-wave input, ±10Vp-p (MAX1270), or ±4.096Vp-p (MAX1271), f
SAMPLE
= 110ksps)
SPECIFICATIONS
Signal-to-Noise + Distortion
Ratio
Total Harmonic Distortion
Spurious-Free Dynamic Range
Channel-to-Channel Crosstalk
Aperture Delay
Aperture Jitter
7-170
SINAD
THD
SFDR
50kHz (Note 3)
DC, V
IN
= ±16.5V
External clock mode
External clock mode
Internal clock mode
Up to the 5th harmonic
80
-86
-96
15
<50
10
70
-87
-78
dB
dB
dB
dB
dB
ns
ps
ns
___________________________________________________________________________________
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +5.0V ±5%; unipolar/bipolar range; external reference mode, V
REF
= +4.096V; 4.7µF at REF; external clock, f
CLK
= 2.0MHz
(50% duty cycle), 18 clock/conversion cycle, 110ksps; T
A
= T
MIN
to T
MAX
; unless otherwise noted. Typical values are T
A
= +25°C.)
PARAMETERS
ANALOG
INPUT
INPUT
Track/Hold Acquisition Time
t
ACQ
f
CLK
= 2.0MHz
±10V or ±V
REF
range
Small-Signal Bandwidth
-3dB
rolloff
±5V or ±V
REF
/
2
range
0 to 10V or 0 to V
REF
range
0 to 5V or 0 to V
REF
/
2
range
Unipolar
(BIP = 0),
Table 3
Input Voltage Range
V
IN
Bipolar
(BIP = 1),
Table 3
MAX1270
MAX1271
MAX1270
MAX1271
Input Current
I
IN
Bipolar
MAX1271
Dynamic Resistance
Input Capacitance
INTERNAL
REFERENCE
INTERNAL
REFERENCE
REF Output Voltage
REF Output Tempco
Output Short Circuit Current
Load Regulation (Note 5)
Capacitive Bypass at REF
Capacitive Bypass at REFADJ
REFADJ Output Voltage
REFADJ Adjustment Range
Buffer Voltage Gain
REFERENCE
INPUT (Reference buffer disabled, reference input applied to REF)
REFERENCE
INPUT
(Reference
Input Voltage Range
Input Current
V
REF
= 4.18V
Normal or STBYPD
FULLPD
2.40
4.18
400
1
V
µA
Figure 1
0 to 0.5mA output current
4.7
0.01
2.465
2.500
±1.5
1.638
2.535
V
REF
TC V
REF
T
A
= +25°C
MAX1270_C/MAX1271_C
MAX1270_E/MAX1271_E
4.076
4.096
±15
±30
30
10
4.116
V
ppm/°C
mA
mV
µF
µF
V
%
V/V
∆V
IN
/∆I
IN
Unipolar
Bipolar
(Note 4)
MAX1270
±10V range
±5V range
±V
REF
range
±V
REF
/2 range
MAX1270
MAX1271
RNG = 1
RNG = 0
RNG = 1
RNG = 0
RNG = 1
RNG = 0
RNG = 1
RNG = 0
0 to 10V range
0 to 5V range
0
0
0
0
-10
-5
-V
REF
-V
REF
/2
-10
-10
-10
-1200
-600
-1200
-600
21
16
40
0.1
5
2.5
2.5
1.25
10
5
V
REF
V
REF
/2
10
5
V
REF
V
REF
/2
720
360
10
720
360
10
10
kΩ
pF
µA
V
MHz
3
µs
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX1270/MAX1271
Unipolar
____________________________________________________________________________________
7-171
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
MAX1270/MAX1271
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +5.0V ±5%; unipolar/bipolar range; external reference mode, V
REF
= +4.096V; 4.7µF at REF; external clock, f
CLK
= 2.0MHz
(50% duty cycle), 18 clock/conversion cycle, 110ksps; T
A
= T
MIN
to T
MAX
; unless otherwise noted. Typical values are T
A
= +25°C.)
PARAMETERS
Input Resistance
REFADJ Threshold for Buffer
Disable
POWER
REQUIREMENT
POWER
REQUIREMENT
Supply Voltage
V
DD
Normal
Supply Current
I
DD
Bipolar range
Unipolar range
6
700
120
±0.1
±0.5
4.75
5.25
18
10
850
220
±0.5
V
mA
µA
LSB
SYMBOL
V
REF
= 4.18V
CONDITIONS
Normal or STBYPD
FULLPD
MIN
10
4.18
V
DD
- 0.5
TYP
MAX
UNITS
kΩ
MΩ
V
STBYPD power down mode (Note 6)
FULLPD power down mode
External reference = 4.096V
Internal reference
Power-Supply Rejection
Ratio (Note 7)
TIMING
External Clock Frequency
Range
Acquisition Phase
Conversion Time
Throughput Rate
Bandgap Reference Start-Up
Time (Note 9)
Reference Buffer Settling Time
PSRR
f
CLK
External clock mode (Note 8)
Internal clock mode, Figure 9
t
CONV
External clock mode (Note 8)
Internal clock mode, Figure 9
External clock mode
Internal clock mode
Power-up
To 0.1mV, REF
bypass capacitor
fully discharged
V
IH
V
IL
V
HYS
I
IN
C
IN
V
IN
= 0 to V
DD
(Note 4)
I
SINK
= 5mA
I
SINK
= 16mA
I
SOURCE
= 0.5mA
CS
= V
DD
CS
= V
DD
(Note 4)
C
REF
= 4.7µF
C
REF
= 33µF
0.1
3
3
6
6
7.7
2.0
MHz
µs
µs
ksps
µs
5
11
110
43
200
8
ms
60
DIGITAL
INPUTS: DIN, SCLK,
CS, SHDN
INPUTS: DIN, SCLK,
Input High Threshold Voltage
Input Low Threshold Voltage
Input Hysteresis
Input Leakage Current
Input Capacitance
DIGITAL
OUTPUTS: DOUT,
SSTRB
OUTPUTS: DOUT,
Output Voltage Low
Output Voltage High
Three-State Leakage Current
Three-State Output Capacitance
V
OL
V
OH
I
L
C
OUT
0.4
0.4
V
DD
- 0.5
-10
10
15
V
V
µA
pF
2.4
0.8
0.2
-10
10
15
V
V
V
µA
pF
7-172
___________________________________________________________________________________
Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
TIMING CHARACTERISTICS
(V
DD
= +4.75V to +5.25; unipolar/bipolar range; external reference mode, V
REF
= +4.096V; 4.7µF at REF; external clock, f
CLK
=
2MHz; T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are T
A
= +25°C.) (Figures 2, 5, 7, 10)
PARAMETERS
DIN to SCLK Setup
DIN to SCLK Hold
SCLK Fall to Output Data Valid
CS
Fall to Output Enable
CS
Rise to Output Disable
CS
to SCLK Rise Setup
CS
to SCLK Rise Hold
SCLK Pulse Width High
SCLK Pulse Width Low
SCLK Fall to SSTRB
CS
to SSTRB Output Enable
CS
to SSTRB Output Disable
SSTRB Rise to SCLK Rise
(Note 4)
SYMBOL
t
DS
t
DH
t
DO
t
DV
t
TR
t
CSS
t
CSH
t
CH
t
CL
t
SSTRB
t
SDV
t
STR
t
SCK
C
LOAD
= 100pF
C
LOAD
= 100pF
External clock mode only
C
LOAD
= 100pF
External clock mode only
Internal clock mode only
0
C
LOAD
= 100pF
C
LOAD
= 100pF
C
LOAD
= 100pF
100
0
200
200
200
200
200
20
CONDITIONS
MIN
100
0
170
120
100
TYP
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MAX1270/MAX1271
Note 1:
Accuracy specifications tested at V
DD
= +5.0V. Performance at power-supply tolerance limit is guaranteed by Power-Supply
Rejection test.
Note 2:
External reference: V
REF
= 4.096V, offset error nulled. Ideal last-code transition = FS - 3/2LSB.
Note 3:
Ground “on” channel; sine wave applied to all “off” channels. V
IN
= ±5V (MAX1270), V
IN
= ±4V (MAX1271).
Note 4:
Guaranteed by design, not production tested.
Note 5:
Use static external loads during conversion for specified accuracy.
Note 6:
Tested using internal reference.
Note 7:
PSRR measured at full scale. Tested for the ±10V (MAX1270) and ±4.096V (MAX1271) input ranges.
Note 8:
Acquisition phase and conversion time are dependent on the clock period; clock has 50% duty cycle (Figure 6).
Note 9:
Not production tested. Provided for design guidance only.
____________________________________________________________________________________
7-173

Plik z chomika:

Inne pliki z tego folderu:

Inne foldery tego chomika:

Zgłoś jeśli naruszono regulamin