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19-4767; Rev 2; 1/99
NUAL
KIT MA
ATION
ET
EVALU
TA SHE
WS DA
FOLLO
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with LVDS Outputs
Features
o
Single +3.3V Supply
o
2.488Gbps Serial to 155Mbps Parallel Conversion
o
660mW Operating Power
o
LVDS Data Outputs and Synchronization Inputs
o
Self-Biasing PECL Inputs Ease AC Coupling
o
Synchronization Inputs for Data Realignment and
Reframing
General Description
The MAX3885 deserializer is ideal for converting
2.488Gbps serial data to 16-bit wide, 155Mbps parallel
data in SDH/SONET applications. Operating from a sin-
gle +3.3V supply, this device accepts PECL serial
clock and data inputs, and delivers low-voltage differ-
ential-signal (LVDS) clock and data outputs for interfac-
ing with high-speed digital circuitry. It also provides an
LVDS synchronization input that enables data realign-
ment and reframing. The MAX3885 is available in the
extended temperature range (-40°C to +85°C) in a 64-
pin TQFP package.
MAX3885
Applications
2.488Gbps SDH/SONET Transmission Systems
Add/Drop Multiplexers
Digital Cross Connects
PART
MAX3885ECB
Ordering Information
TEMP. RANGE
-40°C to +85°C
PIN-PACKAGE
64 TQFP
Pin Configuration appears at end of data sheet.
Typical Operating Circuit
V
CC
= +3.3V
V
CC
= +3.3V
V
CC
= +3.3V
133Ω
133Ω
SD+
V
CC
PD15+
100Ω*
PD15-
SD-
86.6Ω
SERIAL DATA
INPUTS
DATA
AND
CLOCK
RECOVERY
133Ω
86.6Ω
•
•
•
MAX3875
OVERHEAD
TERMINATION
MAX3885
PD0+
V
CC
= +3.3V
PD0-
133Ω
SCLK+
SCLK-
86.6Ω
86.6Ω
PCLK-
SYNC+
SYNC-
GND
PCLK+
100Ω*
100Ω*
*REQUIRED ONLY IF OVERHEAD CIRCUIT DOES NOT INCLUDE INTERNAL INPUT TERMINATION.
THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE Z
0
= 50Ω.
________________________________________________________________
Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with LVDS Outputs
MAX3885
ABSOLUTE MAXIMUM RATINGS
Positive Supply Voltage (V
CC
)...............................-0.5V to +7.0V
Input Voltage Level (all inputs)...................-0.5V to (V
CC
+ 0.5V)
Output Current LVDS outputs .............................................10mA
Continuous Power Dissipation (T
A
= +85°C)
TQFP (derate 24mW/°C above +85°C) .......................1000mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-60°C to +160°C
Lead Temperature (soldering, 10sec) .............................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +3.6V, differential loads = 100Ω ±1%, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at V
CC
= +3.3V,
T
A
= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
UNITS
MIN
TYP
MAX
Supply Current
PECL INPUTS
(SD+/-, SCLK+/-)
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Voltage Range
Differential Input Threshold
Threshold Hysteresis
Differential Input Resistance
Output High Voltage
Output Low Voltage
Differential Output Voltage
Change in Magnitude of Differential
Output Voltage for Complementary
States
Output Offset Voltage
Change in Magnitude of Output
Offset Voltage for Complementary
States
Single-Ended Output Resistance
Change in Magnitude of Single-
Ended Output Resistance for
Complementary Outputs
V
IH
V
IL
I
IH
I
IL
V
I
V
IDTH
V
HYST
R
IN
V
OH
V
OL
V
OD
∆
V
OD
V
OS
∆V
OS
R
O
∆R
O
40
95
±2.5
1.125
0.925
Figure 1
250
400
±25
1.275
±25
140
±10
85
V
IN
= V
IH(MAX)
V
IN
= V
IL(MIN)
Differential input voltage = 100mV
Common-mode voltage = 50mV
V
CC
- 1.16
V
CC
- 1.81
-900
-900
0
-100
78
100
115
1.475
V
CC
- 0.88
V
CC
- 1.48
900
900
2.4
100
V
V
µA
µA
V
mV
mV
Ω
V
V
mV
mV
V
mV
Ω
%
I
CC
200
280
mA
LVDS INPUTS AND OUTPUTS
(SYNC+/-, PCLK+/-, PD_+/-)
AC ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +3.6V, differential loads = 100Ω ±1%, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at V
CC
= +3.3V,
T
A
= +25°C.) (Note 1, Figure 4)
PARAMETER
Maximum Serial Clock Frequency
Serial Data Setup Time
Serial Data Hold Time
Parallel Clock-to-Data Output Delay
SYMBOL
f
SCLK
t
SU
t
H
t
CLK-Q
CONDITIONS
MIN
2.488
100
100
200
450
900
TYP
MAX
UNITS
GHz
ps
ps
ps
Note 1:
AC Characteristics guaranteed by design and characterization.
2
_______________________________________________________________________________________
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with LVDS Outputs
Typical Operating Characteristics
(V
CC
= +3.3V, T
A
= +25°C, unless otherwise noted.)
MAX3885
MAXIMUM SERIAL CLOCK FREQUENCY
vs. TEMPERATURE
MAX3885-01
SERIAL DATA-SETUP TIME
vs. TEMPERATURE
MAX3885-02
SERIAL DATA-HOLD TIME
vs. TEMPERATURE
MAX3885-03
4.4
MAX SERIAL CLOCK FREQUENCY (GHz)
V
CC
= 3.6V
4.3
V
CC
= 3V
4.2
100
SERIAL DATA-SETUP TIME (ps)
0
80
SERIAL DATA-HOLD TIME (ps)
-20
60
-40
40
-60
4.1
20
-80
4.0
-50
-25
0
25
50
75
100
TEMPERATURE (°C)
0
-50
-25
0
25
50
75
100
TEMPERATURE (°C)
-100
-50
-25
0
25
50
75
100
TEMPERATURE (°C)
SUPPLY CURRENT vs. TEMPERATURE
MAX3885-04
PARALLEL CLOCK TO DATA OUTPUT
PROPAGATION DELAY vs. TEMPERATURE
PCLK TO DATA OUTPUT PROPAGATION DELAY (ps)
MAX3885-05
300
700
SUPPLY CURRENT (mA)
250
V
CC
= 3.6V
200
V
CC
= 3V
600
500
400
150
300
100
-50
-25
0
25
50
75
100
TEMPERATURE (°C)
200
-50
-25
0
25
50
75
100
TEMPERATURE (°C)
_______________________________________________________________________________________
3
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with LVDS Outputs
MAX3885
Pin Description
PIN
1, 2, 8, 16, 17,
24, 32, 33, 41,
48, 49, 57, 64
3, 5, 7, 9, 11,
13, 25, 34, 42,
47, 56
4
6
10
12
14
15
18
19
20, 22, 26, 28,
30, 35, 37, 39,
43, 45, 50, 52,
54, 58, 60, 62
21, 23, 27, 29,
31, 36, 38, 40,
44, 46, 51, 53,
55, 59, 61, 63
NAME
GND
Ground
FUNCTION
V
CC
+3.3V Supply Voltage
Serial Data Noninverting PECL Input. Data is clocked on the SCLK signal’s positive transi-
tion.
Serial Data Inverting PECL Input. Data is clocked on the SCLK signal’s positive transition.
Serial Clock Noninverting PECL Input
Serial Clock Inverting PECL Input
Synchronizing Pulse Inverting LVDS Input. Pulse the SYNC signal high for at least four SCLK
periods to shift the data alignment by dropping one bit.
Synchronizing Pulse Noninverting LVDS Input. Pulse the SYNC signal high for at least four
SCLK periods to shift the data alignment by dropping one bit.
Parallel Clock Inverting LVDS Output
Parallel Clock Noninverting LVDS Output
Parallel Data Inverting LVDS Outputs. Data is updated on the negative transition of the PCLK
signal.
SD+
SD-
SCLK+
SCLK-
SYNC-
SYNC+
PCLK-
PCLK+
PD0- to PD15-
PD0+ to PD15+
Parallel Data Noninverting LVDS Outputs. Data is updated on the negative transition of the
PCLK signal.
PD+
D
PD-
V
PD-
SINGLE-ENDED OUTPUT
V
PD+
V
OH
R
L
= 100Ω
V
V
OD
|
V
OD
|
V
OS
V
OL
V
PD+
- V
PD-
DIFFERENTIAL OUTPUT
0V (DIFF.)
0V
+V
OD
V
OD, P - P
= V
PD+
- V
PD-
-V
OD
Figure 1. Driver Output Levels
4
_______________________________________________________________________________________
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with LVDS Outputs
Detailed Description
The MAX3885 deserializer uses a 16-bit shift register,
16-bit parallel output register, 4-bit counter, PECL input
buffers, and low-voltage differential-signal (LVDS)
input/output buffers to convert 2.488Gbps serial data to
16-bit wide, 155Mbps parallel data (Figure 2). The input
shift register continuously clocks incoming data on the
positive transition of the serial clock (SCLK) input sig-
nal. The 4-bit counter generates a parallel-output clock
(PCLK) by dividing the serial-clock frequency by 16.
The PCLK signal clocks the parallel-output register.
During normal operation, the counter divides the SCLK
frequency by 16, causing the output register to latch
every 16 bits of incoming serial data. The synchroniza-
tion inputs (SYNC+, SYNC-) realign and reframe data.
When the SYNC signal is pulsed high for at least four
SCLK cycles, the parallel output data is delayed by one
SCLK cycle. This realignment is guaranteed to occur
within two complete PCLK cycles of the SYNC signal’s
positive transition. As a result, the first incoming bit of
data during that PCLK cycle is dropped, shifting the
alignment between PCLK and data by one bit. See
Figure 3 for the timing diagram and Figure 4 for the tim-
ing parameters diagram.
MAX3885
SD+
SD-
SCLK+
SCLK-
PECL
PECL
16-BIT
SHIFT
REGISTER
16-BIT
PARALLEL
OUTPUT
REGISTER
LVDS
PD15+
PD15-
PD1+
LVDS
MAX3885
PD1-
PD0+
Low-Voltage Differential-Signal (LVDS)
Inputs and Outputs
The MAX3885 features LVDS inputs and outputs for
interfacing with high-speed digital circuitry. The LVDS
standard is based on the IEEE 1596.3 LVDS specifica-
tion. This technology uses 500mVp-p to 800mVp-p dif-
ferential low-voltage swings to achieve fast transition
times, minimize power dissipation, and improve noise
immunity. The parallel clock and data LVDS outputs
(PCLK+, PCLK-, PD_+, PD_-) require 100Ω differential
LVDS
PD0-
PCLK+
SYNC+
SYNC-
100Ω LVDS
4-BIT
COUNTER
LVDS
PCLK-
Figure 2. Functional Diagram
D15
D14
D13
SCLK
SD
SYNC
PCLK
(LSB) PD0
D0
D16
D32
D48
D65
PD1
•
•
•
(MSB) PD15
TRANSMITTED FIRST
D1
D17
D33
D49
ONE BIT HAS SLIPPED
IN THIS TIME SLICE
D66
D15
D31
D47
D64
D80
Figure 3. Timing Diagram
_______________________________________________________________________________________
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