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System Organization
System Organization
Chapter One
To write even a modest 80x86 assembly language program requires considerable familiarity with the
80x86 family. To write
good
assembly language programs requires a strong knowledge of the underlying
hardware. Unfortunately, the underlying hardware is not consistent. Techniques that are crucial for 8088 pro-
grams may not be useful on Pentium systems. Likewise, programming techniques that provide big perfor-
mance boosts on the Pentium chip may not help at all on an 80486. Fortunately, some programming
techniques work well no matter which microprocessor you’re using. This chapter discusses the effect hard-
ware has on the performance of computer software.
1.1
Chapter Overview
This chapter describes the basic components that make up a computer system: the CPU, memory, I/O,
and the bus that connects them. Although you can write software that is ignorant of these concepts, high per-
formance software requires a complete understanding of this material. This chapter also discusses the 80x86
memory addressing modes and how you access memory data from your programs.
This chapter begins by discussing bus organization and memory organization. These two hardware com-
ponents will probably have a bigger performance impact on your software than the CPU’s speed. Under-
standing the organization of the system bus will allow you to design data structures and algorithms that
operate at maximum speed. Similarly, knowing about memory performance characteristics, data locality, and
cache operation can help you design software that runs as fast as possible. Of course, if you’re not interested
in writing code that runs as fast as possible, you can skip this discussion; however, most people do care
about speed at one point or another, so learning this information is useful.
With the generic hardware issues out of the way, this chapter then discusses the program-visible compo-
nents of the memory architecture - specifically the 80x86 addressing modes and how a program can access
memory. In addition to the addressing modes, this chapter introduces several new 80x86 instructions that
are quite useful for manipulating memory. This chapter also presents several new HLA Standard Library
calls you can use to allocate and deallocate memory.
Some might argue that this chapter gets too involved with computer architecture. They feel such mate-
rial should appear in an architectural book, not an assembly language programming book. This couldn’t be
farther from the truth! Writing
good
assembly language programs requires a strong knowledge of the archi-
tecture. Hence the emphasis on computer architecture in this chapter.
1.2
The Basic System Components
The basic operational design of a computer system is called its
architecture
. John Von Neumann, a pio-
neer in computer design, is given credit for the architecture of most computers in use today. For example, the
80x86 family uses the
Von Neumann architecture
(VNA). A typical Von Neumann system has three major
components: the
central processing unit
(or
CPU
),
memory,
and
input/output
(or
I/O
). The way a system
designer combines these components impacts system performance (See Figure 1.1).
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Chapter One
Volume Two
Memory
CPU
I/O Devices
Figure 1.1
Typical Von Neumann Machine
In VNA machines, like the 80x86 family, the CPU is where all the action takes place. All computations
occur inside the CPU. Data and machine instructions reside in memory until required by the CPU. To the
CPU, most I/O devices look like memory because the CPU can store data to an output device and read data
from an input device. The major difference between memory and I/O locations is the fact that I/O locations
are generally associated with external devices in the outside world.
1.2.1 The System Bus
The
system bus
connects the various components of a VNA machine. The 80x86 family has three major
busses: the
address
bus, the
data
bus, and the
control
bus. A bus is a collection of wires on which electrical
signals pass between components in the system. These busses vary from processor to processor. However,
each bus carries comparable information on all processors; e.g., the data bus may have a different implemen-
tation on the 80386 than on the 8088, but both carry data between the processor, I/O, and memory.
A typical 80x86 system component uses
standard TTL logic levels
1
.
This means each wire on a bus
uses a standard voltage level to represent zero and one
2
. We will always specify zero and one rather than the
electrical levels because these levels vary on different processors (especially laptops).
1.2.1.1
The Data Bus
The 80x86 processors use the
data bus
to shuffle data between the various components in a computer
system. The size of this bus varies widely in the 80x86 family. Indeed, this bus defines the “size” of the pro-
cessor.
Every modern x86 CPU from the Pentium on up employs a 64-bit wide data bus. Some of the earlier
processors used 8-bit, 16-bit, or 32-bit data busses, but such machines are sufficiently obsolete that we do
not need to consider them here..
1. Actually, newer members of the family tend to use lower voltage signals, but these remain compatible with TTL signals.
2. TTL logic represents the value zero with a voltage in the range 0.0-0.8v. It represents a one with a voltage in the range
2.4-5v. If the signal on a bus line is between 0.8v and 2.4v, it’s value is indeterminate. Such a condition should only exist
when a bus line is changing from one state to the other.
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System Organization
You’ll often hear a processor called an
eight, 16, 32, or 64 bit processor.
While there is a mild contro-
versy concerning the size of a processor, most people now agree that the minimum of either the number of
data lines on the processor or the size of the largest general purpose integer register determines the processor
size. The modern x86 CPUs all have 64-bit busses, but only provide 32-bit general purpose integer registers,
so most people classify these devices as 32-bit processors.
Although the 80x86 family members with eight, 16, 32, and 64 bit data busses
can
process data up to
the width of the bus, they can also access smaller memory units of eight, 16, or 32 bits. Therefore, anything
you can do with a small data bus can be done with a larger data bus as well; the larger data bus, however,
may access memory faster and can access larger chunks of data in one memory operation. You’ll read about
the exact nature of these memory accesses a little later (see “The Memory Subsystem” on page 140).
1.2.1.2
The Address Bus
The data bus on an 80x86 family processor transfers information between a particular memory location
or I/O device and the CPU. The only question is, “Which
memory location or I/O device?
” The address bus
answers that question. To differentiate memory locations and I/O devices, the system designer assigns a
unique memory address to each memory element and I/O device. When the software wants to access some
particular memory location or I/O device, it places the corresponding address on the address bus. Circuitry
associated with the memory or I/O device recognizes this address and instructs the memory or I/O device to
read the data from or place data on to the data bus. In either case, all other memory locations ignore the
request. Only the device whose address matches the value on the address bus responds.
With a single address line, a processor could create exactly two unique addresses: zero and one. With
n
address lines, the processor can provide 2
n
unique addresses (since there are 2
n
unique values in an
n-bit
binary number). Therefore, the number of bits on the address bus will determine the
maximum
number of
addressable memory and I/O locations. Early x86 processors, for example, provided only 20 bit address bus-
ses. Therefore, they could only access up to 1,048,576 (or 2
20
) memory locations. Larger address busses can
access more memory.
Table 12: 80x86 Family Address Bus Sizes
Processor
8088, 8086, 80186,
80188
80286, 80386sx
80386dx
80486, Pentium
Pentium Pro, II, III, IV
Address Bus
Size
20
24
32
32
36
Max Addressable
Memory
1,048,576
16,777,216
4,294,976,296
4,294,976,296
68,719,476,736
In English!
One Megabyte
Sixteen Megabytes
Four Gigabytes
Four Gigabytes
64 Gigabytes
Future 80x86 processors (e.g., the AMD “Hammer”) will probably support 40, 48, and 64-bit address
busses. The time is coming when most programmers will consider four gigabytes of storage to be too small,
much like they consider one megabyte insufficient today. (There was a time when one megabyte was consid-
ered far more than anyone would ever need!).
1.2.1.3
The Control Bus
The control bus is an eclectic collection of signals that control how the processor communicates with
the rest of the system. Consider for a moment the data bus. The CPU sends data to memory and receives data
from memory on the data bus. This prompts the question, “Is it sending or receiving?” There are two lines on
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Chapter One
Volume Two
the control bus,
read
and
write,
which specify the direction of data flow. Other signals include system clocks,
interrupt lines, status lines, and so on. The exact make up of the control bus varies among processors in the
80x86 family. However, some control lines are common to all processors and are worth a brief mention.
The
read
and
write
control lines control the direction of data on the data bus. When both contain a logic
one, the CPU and memory-I/O are not communicating with one another. If the read line is low (logic zero),
the CPU is reading data from memory (that is, the system is transferring data from memory to the CPU). If
the write line is low, the system transfers data from the CPU to memory.
The
byte enable lines
are another set of important control lines. These control lines allow 16, 32, and 64
bit processors to deal with smaller chunks of data. Additional details appear in the next section.
The 80x86 family, unlike many other processors, provides two distinct address spaces: one for memory
and one for I/O. While the memory address busses on various 80x86 processors vary in size, the I/O address
bus on all 80x86 CPUs is 16 bits wide. This allows the processor to address up to 65,536 different I/O
loca-
tions.
As it turns out, most devices (like the keyboard, printer, disk drives, etc.) require more than one I/O
location. Nonetheless, 65,536 I/O locations are more than sufficient for most applications. The original IBM
PC design only allowed the use of 1,024 of these.
Although the 80x86 family supports two address spaces, it does not have two address busses (for I/O
and memory). Instead, the system shares the address bus for both I/O and memory addresses. Additional
control lines decide whether the address is intended for memory or I/O. When such signals are active, the I/O
devices use the address on the L.O. 16 bits of the address bus. When inactive, the I/O devices ignore the sig-
nals on the address bus (the memory subsystem takes over at that point).
1.2.2 The Memory Subsystem
A typical 80x86 processor addresses a maximum of 2
n
different memory locations, where
n
is the num-
ber of bits on the address bus
3
. As you’ve seen already, 80x86 processors have 20, 24, 32, and 36 bit address
busses (with 64 bits on the way).
Of course, the first question you should ask is, “What exactly is a memory location?” The 80x86 sup-
ports
byte addressable memory.
Therefore, the basic memory unit is a byte. So with 20, 24, 32, and 36
address lines, the 80x86 processors can address one megabyte, 16 megabytes, four gigabytes, and 64
gigabytes of memory, respectively.
Think of memory as a linear array of bytes. The address of the first byte is zero and the address of the
last byte is 2
n
-1. For an 8088 with a 20 bit address bus, the following pseudo-Pascal array declaration is a
good approximation of memory:
Memory: array [0..1048575] of byte;
To execute the equivalent of the Pascal statement “Memory [125] := 0;” the CPU places the value zero
on the data bus, the address 125 on the address bus, and asserts the write line (since the CPU is writing data
to memory), see Figure 1.2.
3. This is the
maximum.
Most computer systems built around 80x86 family do not include the maximum addressable amount
of memory.
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System Organization
Address = 125
Memory
CPU
Data = 0
Write = 0
Location
125
Figure 1.2
Memory Write Operation
To execute the equivalent of “CPU := Memory [125];” the CPU places the address 125 on the address
bus, asserts the read line (since the CPU is reading data from memory), and then reads the resulting data
from the data bus (see Figure 1.3).
Address = 125
Memory
CPU
Data = Memory[125]
Location
125
Read = 0
Figure 1.3
Memory Read Operation
The above discussion applies
only
when accessing a single byte in memory. So what happens when the
processor accesses a word or a double word? Since memory consists of an array of bytes, how can we possi-
bly deal with values larger than eight bits?
Different computer systems have different solutions to this problem. The 80x86 family deals with this
problem by storing the L.O. byte of a word at the address specified and the H.O. byte at the next location.
Therefore, a word consumes two consecutive memory addresses (as you would expect, since a word consists
of two bytes). Similarly, a double word consumes four consecutive memory locations. The address for the
double word is the address of its L.O. byte. The remaining three bytes follow this L.O. byte, with the H.O.
byte appearing at the address of the double word
plus three
(see Figure 1.4). Bytes, words, and double
words may begin at
any
valid address in memory. We will soon see, however, that starting larger objects at
an arbitrary address is not a good idea.
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