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Features

•

8-Bit CPU Optimized for Control Applications

•

Extensive Boolean Processing Capabilities (Single-Bit Logic)

•

On-Chip Flash Program Memory

•

On-Chip Data RAM

•

Bidirectional and Individually Addressable I/O Lines

•

Multiple 16-Bit Timer/Counters

•

Full Duplex UART

•

Multiple Source/Vector/Priority Interrupt Structure

•

On-Chip Clock Oscillator

•

On-chip EEPROM (AT89S series)

•

SPI Serial Bus Interface (AT89S Series)

•

Watchdog Timer (AT89S Series)

The basic architectural structure of the AT89C51 core is shown in Figure 1.

Flash

Microcontroller

Architectural

Overview

Block Diagram

Figure 1.

Block Diagram of the AT89C core

EXTERNAL

INTERRUPTS

ETC.

ON-CHIP

FLASH

TIMER 1

ON-CHIP

RAM

INTERRUPT

CONTROL

TIMER 0

COUNTER

INPUTS

CPU

OSC

BUS

CONTROL

4 I/O PORTS

SERIAL

PORT

TXD

RXD

ADDRESS/DATA

For more information on the individual devices and features, refer to the Hardware

Descriptions and Data Sheets of the specific device.

0497B-B–12/97

2-3

Figure 2.

Block Diagram of the AT89S core

Figure 3.

AT89C51/LV51 and AT89C52/LV52 Memory Structure

PROGRAM MEMORY

(READ ONLY)

FFFFH:

DATA MEMORY

(READ/WRITE)

FFFFH:

EXTERNAL

INTERNAL

FFH:

EA = 0

EXTERNAL

EA = 1

INTERNAL

0000

PSEN

RD WR

2-4

Architectural Overview

Architectural Overview

Reduced Power Modes

To exploit the power savings available in CMOS circuitry,

Atmel’s Flash microcontrollers have two software-invoked

reduced power modes.

• Idle Mode. The CPU is turned off while the RAM and

other on-chip peripherals continue operating. In this

mode, current draw is reduced to about 15 percent of the

current drawn when the device is fully active.

• Power Down Mode. All on-chip activities are suspended,

while the on-chip RAM continues to hold its data. In this

mode, the device typically draws less than 15

µA,

and

can be as low as 0.6

µA.

In addition, these devices are designed using static logic,

which does not require continuous clocking. That is, the

clock frequency can be slowed or even stopped while wait-

ing for an internal event.

The interrupt service locations are spaced at 8-byte inter-

vals: 0003H for External Interrupt 0, 000BH for Timer 0,

0013H for External Interrupt 1, 001BH for Timer 1, and so

on. If an interrupt service routine is short enough (as is

often the case in control applications), it can reside entirely

within that 8-byte interval. Longer service routines can use

a jump instruction to skip over subsequent interrupt loca-

tions, if other interrupts are in use.

The lowest addresses of program memory can be either in

the on-chip Flash or in an external memory. To make this

selection, strap the External Access (EA) pin to either V

or GND.

For example, in the AT89C51 with 4K bytes of on-chip

Flash, if the EA pin is strapped to V

, program fetches to

addresses 0000H through 0FFFH are directed to the inter-

nal Flash. Program fetches to addresses 1000H through

FFFFH are directed to external memory.

In the AT89C52 (8K bytes Flash), EA = V

selects

addresses 0000H through 1FFFH to be internal and

addresses 2000H through FFFFH to be external.

If the EA pin is strapped to GND, all program fetches are

directed to external memory.

The read strobe to external memory, PSEN, is used for all

external program fetches. Internal program fetches do not

activate PSEN.

The hardware configuration for external program execution

is shown in Figure 5. Note that 16 I/O lines (Ports 0 and 2)

are dedicated to bus functions during external program

memory fetches. Port 0 (P0 in Figure 5) serves as a multi-

plexed address/data bus. It emits the low byte of the Pro-

gram Counter (PCL) as an address and then goes into a

float state while waiting for the arrival of the code byte from

the program memory. During the time that the low byte of

the Program Counter is valid on P0, the signal ALE

(Address Latch Enable) clocks this byte into an address

latch. Meanwhile, Port 2 (P2 in Figure 5) emits the high

byte of the Program Counter (PCH). Then PSEN strobes

the external memory, and the microcontroller reads the

code byte.

Figure 4.

Program Memory

Memory Organization

Logical Separation of Program Data Memory

All Atmel Flash microcontrollers have separate address

spaces for program and data memory, as shown in Figure

3. The logical separation of program and data memory

allows the data memory to be accessed by 8-bit addresses,

which can be more quickly stored and manipulated by an 8-

bit CPU. Nevertheless, 16-bit data memory addresses can

also be generated through the DPTR register.

Program memory can only be read. There can be up to 64K

bytes of directly addressable program memory. The read

strobe for external program memory is the Program Store

Enable signal (PSEN).

Data memory occupies a separate address space from pro-

gram memory. Up to 64K bytes of external memory can be

directly addressed in the external data memory space. The

CPU generates read and write signals, RD and WR, during

external data memory accesses.

External program memory and external data memory can

be combined by applying the RD and PSEN signals to the

input of an AND gate and using the output of the gate as

the read strobe to the external program/data memory.

Program Memory

Figure 4 shows a map of the lower part of the program

memory. After reset, the CPU begins execution from loca-

tion 0000H.

As shown in Figure 4, each interrupt is assigned a fixed

location in program memory. The interrupt causes the CPU

to jump to that location, where it executes the service rou-

tine. External Interrupt 0, for example, is assigned to loca-

tion 0003H. If External Interrupt 0 is used, its service rou-

tine must begin at location 0003H. If the interrupt is not

used, its service location is available as general purpose

program memory.

2-5

Program memory addresses are always 16 bits wide, even

though the actual amount of program memory used may be

less than 64K bytes. External program execution sacrifices

two of the 8-bit ports, P0 and P2, to the function of address-

ing the program memory.

Figure 5.

Executing from External Program Memory

AT89

EXTERNAL

PROGRAM

MEMORY

ALE

LATCH

PSEN

ADDR

INSTR.

Internal data memory is shown in Figure 7. The memory

space is divided into three blocks, which are generally

referred to as the Lower 128, the Upper 128, and SFR

space.

Figure 7.

Internal Data Memory

FFH

UPPER

128

80H

7FH

LOWER

128

ACCESSIBLE

BY DIRECT

AND INDIRECT

ADDRESSING

ACCESSIBLE

BY INDIRECT

ADDRESSING

ONLY

ACCESSIBLE

BY DIRECT

ADDRESSING

80H

SPECIAL

FUNCTION

REGISTERS

PORTS

STATUS AND

CONTROL BITS

TIMERS

REGISTERS

STACK POINTER

ACCUMULATOR

(ETC.)

FFH

Data Memory

The right half of Figure 3 shows the internal and external

data memory spaces available on Atmel’s Flash microcon-

trollers.

Figure 6 shows a hardware configuration for accessing up

to 2K bytes of external RAM. In this case, the CPU exe-

cutes from internal Flash. Port 0 serves as a multiplexed

address/data bus to the RAM, and 3 lines of Port 2 are

used to page the RAM. The CPU generates RD and WR

signals as needed during external RAM accesses.

You can assign up to 64K bytes of external data memory.

External data memory addresses can be either 1 or 2 bytes

wide. One-byte addresses are often used in conjunction

with one or more other I/O lines to page the RAM, as

shown in Figure 6. Two-byte addresses can also be used,

in which case the high address byte is emitted at Port 2.

Figure 6.

Accessing external data memory. If the program

memory is internal, the other bits of P2 are available as I/O.

Internal data memory addresses are always 1 byte wide,

which implies an address space of only 256 bytes. How-

ever, the addressing modes for internal RAM can in fact

accommodate 384 bytes. Direct addresses higher than

7FH access one memory space, and indirect addresses

higher than 7FH access a different memory space. Thus,

Figure 7 shows the Upper 128 and SFR space occupying

the same block of addresses, 80H through FFH, although

they are physically separate entities.

Figure 8 shows how the lower 128 bytes of RAM are

mapped. The lowest 32 bytes are grouped into 4 banks of 8

registers. Program instructions call out these registers as

R0 through R7. Two bits in the Program Status Word

(PSW) select which register bank is in use. This architec-

ture allows more efficient use of code space, since register

instructions are shorter than instructions that use direct

addressing.

Figure 8.

The Lower 128 Bytes of Internal RAM

7FH

SCRATCH PAD

AREA

30H

AT89

WITH

INTERNAL

P1 FLASH P0

ALE

LATCH

ADDR

VCC

EXTERNAL

DATA

MEMORY

DATA

2FH

BANK

SELECT

BITS IN

PSW

BIT-ADDRESSABLE SPACE

(BIT ADDRESSES 0-7F)

20H

{

1FH

18H

17H

10H

0FH

08H

07H

RESET VALUE OF

STACK POINTER

4 BANKS OF

8 REGISTERS

R0-R7

P3 P2

I/O

PAGE

BITS

2-6

Architectural Overview

Architectural Overview

The next 16 bytes above the register banks form a block of

bit-addressable memory space. The microcontroller

instruction set includes a wide selection of single-bit

instructions, and these instructions can directly address the

128 bits in this area. These bit addresses are 00H through

7FH.

All of the bytes in the Lower 128 can be accessed by either

direct or indirect addressing. The Upper 128 (Figure 9) can

only be accessed by indirect addressing. The Upper 128

bytes of RAM are only in the devices with 256 bytes of

RAM.

Figure 9.

The Upper 128 Bytes of Internal RAM

Byte

address

Bit address

Figure 10 gives a brief look at the Special Function Regis-

ter (SFR) space. SFRs include Port latches, timers, periph-

eral controls, etc. These registers can only be accessed by

direct addressing. In general, all Atmel microcontrollers

have the same SFRs at the same addresses in SFR space

as the AT89C51 and other compatible microcontrollers.

However, upgrades to the AT89C51 have additional SFRs.

Sixteen addresses in SFR space are both byte- and bit-

addressable. The bit-addressable SFRs are those whose

address ends in 000B. The bit addresses in this area are

80H through FFH.

Figure 10.

SFR Space

Byte

address

Bit address

F7 F6 F5 F4 F3 F2 F1 F0

E7 E6 E5 E4 E3 E2 E1 E0

D7 D6 D5 D4 D3 D2

ACC

PSW

SBUF

SCON

TH1

TH0

TL1

TL0

TMOD

TCON

PCON

DPH

DPL

General

purpose

RAM

BC BB BA B9 B8

B7 B6 B5 B4 B3 B2 B1 B0

AC AB AA A9 A8

A7 A6 A5 A4 A3 A2 A1 A0

not bit addressable

9F 9E 9D 9C 9B 9A 99 98

97 96 95 94 93 92 91 90

not bit addressable

8F 8E 8D 8C 8B 8A 89 88

not bit addressable

87 86 85 84 83 82 81 80

Special Function Registers

Bit-addressable locations

Bank 3

Bank 2

Bank 1

Default register

bank for R0-R7

RAM

2-7

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