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AN555
Transmission of a byte is performed by calling the
PutChar
function and the data byte in the TxReg is
transmitted out. Before calling this function (
PutChar
),
the data must be loaded into TxReg and ensure the
serial port is free. The serial port is free when both the
_txmtProgress and the _rcvOver bits are cleared (see
description of these bits in the Serial Status/Control
Reg table given later).
Software Implementation of Asynchronous Serial I/O
Amar Palacherla
Microchip Technology
Scott Fink
Microchip Technology Inc.
INTRODUCTION
PIC16CXXX microcontrollers from Microchip Technology,
Inc., high-performance, EPROM-based 8-bit microcon-
trollers. Some of the members of this series (like the
PIC16C71 and PIC16C84) do not have an on-chip hard-
ware asynchronous serial port. This application note
describes the interrupt driven software implementation of
Asynchronous Serial I/O (Half Duplex RS-232 Communi-
cations) using PIC16CXXX microcontrollers. These
microcontrollers can operate at very high speeds with a
minimum of 250 ns cycle time (with input clock frequency
of 16 MHz). To test the RS-232 routines, a simple Digital
Voltmeter (DVM)/Analog Data Acquisition System has
been implemented using a PIC16C71, in which, upon
reception of a command from host (IBM PC-AT
®
), an 8-bit
value of the selected A/D channel is transmitted back to
the host.
Summary of
PutChar
function:
1.
2.
3.
Make sure _txmtProgress & _rcvOver bits are
cleared
Load TxReg with data to be transmitted
Call
PutChar
function
Receive Mode
The reception mode implementation is slightly different
from the transmit mode. Unlike the transmit pin (TX in
the example code is RB7, but could be any I/O pin), the
receive pin (RX) must be connected to pin RA4/T0CKI.
This is because, in reception, the Start Bit, which is
asynchronous in nature, must be detected. To detect
the Start bit, when put in Reception mode, the Timer0
module is configured to Counter mode. The OPTION
register is configured so the Timer0 module is put in
Counter mode (increment on external clock on
RA4/T0CKI Pin) and set to increment on the falling
edge of pin RA4/T0CKI with no prescaler assigned.
After this configuration setup, TMR0 (File Reg 1) is
loaded with 0xFF. A falling edge on the T0CKI pin
makes TMR0 roll over from 0xFF to 0x00, thus gener-
ating an interrupt indicating a Start Bit. The RA4/T0CKI
pin is sampled again to make sure the transition on
TMR0 is not a glitch. Once the start bit has been
detected, the Timer0 module is reconfigured to incre-
ment on internal clock and the prescaler is assigned to
it depending on input master clock frequency and the
baud rate (configured same way as the transmission
mode).
The software serial port is put in reception mode when
a call is made to function
GetChar
. Before calling this
function make sure the serial port is free (i.e.,
_txmtProgress and _rcvOver status bits must be '0').
On completion of a reception of a byte, the data is
stored in RxReg and the _rcvOver bit is cleared.
IMPLEMENTATION
A half duplex, interrupt driven, software implementation of
RS-232 communications, using a PIC16C71, is described
in detail below. The transmit pin used in the example code
is RB7 and the receive pin is connected to the RA4/T0CKI
pin (Figure 2). Of course these pins are connected with
appropriate voltage translation to/from RS-232/CMOS
levels. Schematics describe the voltage translation in the
hardware section of this application note.
Transmit Mode
Transmit mode is quite straight-forward to implement in
software using interrupts. Once input clock frequency
and baud rate are known, the number of clock cycles
per bit can be computed. The on-chip Timer0 timer with
its prescaler can be used to generate an interrupt on
TMR0 overflow. This TMR0 overflow interrupt can be
used as timing to send each bit. The Input clock fre-
quency (
_ClkIn
) and Baud Rate (
_BaudRate
) are
programmable by the user and the TMR0 time-out
value (the period for each bit) is computed at assembly
time. Whether the prescaler must be assigned to
Timer0 or not is also determined at assembly time. This
computation is done in the header file
rs232.h
. Note
that very high speed transmissions can be obtained if
transmission is done with “software delays” instead of
being “every interrupt” driven, however, the processor
will be totally dedicated to this job.
Summary of
GetChar
function:
1.
2.
3.
Make sure _txmtProgress & _rcvOver bits are
cleared.
Call
GetChar
function.
The received Byte is in TxReg after the _rcvOver
bit is cleared.
IBM PC-AT is a registered trademark of International Business Machines Corp.
©
1997 Microchip Technology Inc.
DS00555C-page 1
AN555
Parity Generation
Parity can be enabled at assembly time by setting the
“_PARITY_ENABLE” flag to TRUE. If enabled, parity
can be configured to either EVEN or ODD parity. In
transmission mode, if parity is enabled, the parity bit is
computed and transmitted as the ninth bit. On
reception, the parity is computed on the received byte
and compared to the ninth bit received. If a match does
not occur the parity error bit is set in the RS-232
Status/Control Register (_ParityErr bit of SerialStatus
reg). The parity bit is computed using the algorithm
shown in Figure 1. This algorithm is highly efficient
using the PIC16CXXX’s
SWAPF
and
XORWF
instruc-
tions (with ability to have the destination as either the
file register itself or the W register) and the sub-routine
(called
GenParity
) is in file
txmtr.asm
.
FIGURE 1:
AN EFFICIENT PARITY GENERATION SCHEME IN SOFTWARE
Data Byte
Bits <7:4>
Bits <3:0>
<3:2>
XOR
1
XOR
Parity Bit
XOR
0
<1:0>
Assembly Time Options
The firmware is written as a general purpose routine
and the user must specify the parameters shown in
Table 1 before assembling the program. The Sta-
tus/Control register is described in Table 2.
TABLE 1:
_ClkIn
LIST OF ASSEMBLY TIME OPTIONS
Input clock frequency of the processor.
Desired Baud Rate. Any valid value can be used. The highest baud rate achievable
depends on input clock frequency. 600 to 4800 Baud was tested using a 4 MHz Input
Clock. 600 to 19200 Baud was tested using a 10 MHz Input Clock. Higher rates can be
obtained using higher input clock frequencies.
Once the _BaudRate & _ClkIn are specified, the program automatically selects all the
appropriate timings.
Can specify 1 to 8 data bits.
Limited to 1 Stop Bit. Must be set.
Parity Enable Flag. Configure it to TRUE or FALSE. If PARITY is used, then configure it to
TRUE, else FALSE. See “_ODD_PARITY” flag description below.
Configure it to TRUE or FALSE. If TRUE, then ODD PARITY is used, else EVEN Parity
Scheme is used.
This Flag is ignored if _PARITY_ENABLE is configured to FALSE.
RTS & CTS Hardware handshaking signals. If configured to FALSE, no hardware
handshaking is used. If configured to TRUE, RTS & CTS use up 2 I/O Pins of PORTB.
_BaudRate
_DataBits
_StopBits
_PARITY_ENABLE
_ODD_PARITY
_USE_RTSCTS
DS00555C-page 2
©
1997 Microchip Technology Inc.
AN555
TABLE 2:
Bit #
0
1
BIT ASSIGNMENT OF SERIAL STATUS/CONTROL REGISTER
(SERIALSTATUS REG)
Name
_txmtProgres
s
_txmtEnable
1 = Transmission in progress.
0 = Transmission line free.
Set this bit on initialization to enable transmission. This bit may be used to
abort a transmission. The transmission is aborted if in the middle of a
transmission (i.e., when _txmtProgress bit is '1') _txmtEnable bit is cleared.
This bit gets automatically set when the
PutChar
function is called.
1 = Middle of a byte reception.
0 = Reception of a byte (in RxReg) is complete and is set when a valid start
bit is detected in reception mode.
0 = Completion of reception of a byte. The user’s code can poll this bit after
calling the
GetChar
function and check to see if it is set. When set, the
received byte is in RxReg. Other status bits should also be checked for
any reception errors.
1 = Parity error on reception (irrespective of Even Or Odd parity chosen). Not
applicable if No Parity is used.
1 = Framing error on reception.
Unused
_parityBit
The 9th bit of transmission or reception. In transmission mode, the parity bit
of the byte to be transmitted is stored in this bit. In receive mode, the 9th bit
(or parity bit) received is stored in this bit. Not Applicable if no parity is used.
Description
2
_rcvProgress
3
_rcvOver
4
5
6
7
_ParityErr
_FrameErr
©
1997 Microchip Technology Inc.
DS00555C-page 3
AN555
Hardware
The hardware is primarily concerned with voltage trans-
lation from RS-232 to CMOS levels and vice versa.
Three circuits are given below and the user may choose
whichever best applies. The primary difference
between each solution is cost versus number of compo-
nents. Circuits in Figure 3 and Figure 4 are very low
cost but have more components than the circuit in
Figure 2. The circuit in Figure 2 interfaces to a RS-232
line using a single chip (MAX-232) and single +5V sup-
ply. The circuit in Figure 3 is a low cost RS-232 Inter-
face but requires two chips and a single +5V supply
source.
Figure 4 shows a very low cost RS-232 Interface to an
IBM PC-AT with no external power requirements. The
circuit draws power from the RS-232 line (DTR) and
meets the spec of drawing power less than 5 mA. This
requires that for the host to communicate it must assert
lines DTR high and RTS low. The power is drawn from
the DTR line and this requires that DTR be asserted
high and must be at least 7V. The negative -5 to -10V
required by LM339 is drawn from the RTS line and thus
the host must assert RTS low. This circuit is possible
because of the low current consumption of the
PIC16C71 (typical 2 mA).
FIGURE 2:
SINGLE CHIP RS-232 INTERFACE (SINGLE +5V SUPPLY)
0.1
µF
+5V
16
V
DD
T0CKI
RB7
RTS
10
µF,
6.3V
PIC16C71
0.1
µF
3
V
SS
0.1
µF
6
5
15
CTS
12
11
9
10
1
MAX-232A
2
13
14
8
7
6
RX
TX
RTS
CTS
RS-232
Signals
0.1
µF
FIGURE 3:
LOW COST RS-232 INTERFACE (TWO CHIPS, SINGLE +5V SUPPLY)
+5V
V+
OUTB
OUTA
RX (RS-232)
INA
CTS (RS-232)
INB
+5V
TX
B1
B2
TX (RS-232)
RTS (RS-232)
OUTA
OUTB
RX
CTS
MC14C88
RTS
DTR
(Assert DTR low)
A
V-
GND
GND
DS00555C-page 4
©
1997 Microchip Technology Inc.
AN555
FIGURE 4:
LOW COST, LOW POWER RS-232 INTERFACE (POWER SUPPLIED BY RS-232 LINES)
DB9
1
6
BAT 42
DTR
100
µF
LM2936
RS-232
+5V
10
µF
+5V
PIC16CXXX
V
AIN
1k
0.1
µF
+5V
RB7
LM301
10k
10k
-10V
IN4148
TX (Pin 2
of DB9)
RTS (Pin 7
of DB9
T0CKI
RA0
10k
ZVN104
10k
IN4148
RX (Pin 3
of DB9)
Test Program
To test the transmission and reception modules, a main
program is written in which the PIC16C71 waits to
receive a command from a host through the RS-232.
On reception of a byte (valid commands are 0x00,
0x01, 0x02 & 0x03), the received byte is treated as the
PIC16C71’s A/D channel number and the requested
channel is selected. An A/D conversion is started and
when the conversion is complete (in about 20
µ
s) the
digital data (8-bits) is transmitted back to the host. A
Microsoft
®
Windows
®
program running on an
IBM PC/AT was written to act as a host and collect the
A/D data from the PIC16C71 via an RS-232 port. The
Windows program (DVM.EXE) runs as a background
job and displays the A/D data in a small window (similar
to the CLOCK program that comes with MS Windows).
The windows program and the PIC16C71 together act
like a data acquisition system or a digital voltmeter
(DVM). The block diagram of the system is shown in
Figure 2. The input clock frequency is fixed at 4 MHz
and RS-232 parameters are set to 1200 Baud, 8-bits,
1 Stop Bit and No Parity. The program during
development stage was also tested at 1200, 2400,
4800 Baud Rates @ 4 MHz Input Clock and up to
19200 Baud @ 10 MHz input clock frequency (all tests
were performed with No Parity, Even Parity and Odd
Parity at 8 and 7 Data Bits).
FIGURE 5:
MS WINDOWS PROGRAM
FETCHING A/D DATA FROM
PIC16C71 VIA RS-232
PIC16C71:DVM
Chan#0
→
2.52 Volts
Microsoft and Windows are registered trademarks of Microsoft Corp.
©
1997 Microchip Technology Inc.
DS00555C-page 5

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