16.pdf

(2557 KB) Pobierz
Chapter 16
DSP and Software
Radio Design
Digital signal processing (DSP) is one
of the great technological innovations of
the last hundred years. It has found a per-
manent place not only in radio, but also in
the exploration for oil and other fossil
fuels, high-definition television (HDTV),
compact-disc (CD) recording and many
other facets of our lives. Its popularity
stems from certain advantages: DSP fil-
ters do not need tuning and may be exactly
duplicated from unit to unit; temperature
variations are virtually non-existent; and
DSP represents the ultimate in flexibility,
since general-purpose DSP hardware can
be programmed to perform many different
functions, often eliminating other hard-
ware. This chapter was written by Doug
Smith, KF6DX.
DSP FUNDAMENTALS
In this chapter, you will see that DSP is
about rapidly measuring analog signals,
recording the measurements as a series of
numbers, processing those numbers, then
converting the new sequence back to ana-
log signals. How we process the numbers
depends on which of many possible func-
tions we are performing. We will take a
look at some of those functions and ex-
plore how real DSP systems are imple-
mented in software and hardware.
Sampling
The process of generating a sequence of
numbers that represent periodic measure-
ments of a continuous analog waveform is
called
sampling.
Each number in the se-
quence is a single measurement of the in-
stantaneous amplitude of the waveform at
a sampling time. When we make the mea-
surements continually at regular intervals,
the result is a sequence of numbers repre-
senting the amplitude of the signal at
evenly spaced times.
This process is illustrated in
Fig 16.1.
Note that the frequency of the sine wave
being sampled is much less than the
sam-
pling frequency,
f
s
. In other words, we are
taking many samples during each cycle of
Fig 16.1—Sine wave of frequency much less than the sampling frequency (A). The
sampled sine wave (B).
DSP and Software Radio Design
16.1
the sine wave. The sampled waveform
does not contain information about what
the analog signal did between samples, but
it still roughly resembles the sine wave.
Were we to feed the analog sine wave into
a spectrum analyzer, we would see a single
spike at the sine wave’s frequency. Pretty
obviously, the spectrum of the sampled
waveform is not the same, since it is a step-
wise representation.
The sampled signal’s spectrum can be
predicted and interpreted in the following
way. The analog sine wave’s spectrum is
shown in
Fig 16.2A,
above the spectrum of
the sampling function in Fig 16.2B. The
sampled signal is just the
product
of the two
signals; its spectrum is the
convolution
of
the two input spectra, as shown in Fig 16.2C.
The sampling process is equivalent to a mix-
ing process: They each perform a multipli-
cation of the two input signals.
Note that the sampled spectrum repeats
at intervals of f
s
. These repetitions are
called
aliases
and are as real as the funda-
mental in the sampled signal. Each con-
tains all the information necessary to fully
describe the original signal. In general, we
are only interested in the fundamental, but
let’s see what happens when the sampling
frequency is
less than
that of the analog
input.
Sine Wave, Alias Sine Wave:
Harmonic Sampling
Take the case wherein the sampling fre-
quency is less than that of the analog sine
wave. See
Fig 16.3.
The sampled output
no longer matches the input waveform.
Notice that the sampled signal retains the
shape of a sine wave at a frequency lower
than that of the input. Ordinarily, this
would not be a happy situation.
A downward frequency translation is
useful, though, in the design of IF-DSP
receivers. In addition, lower sampling fre-
quencies are good because they allow
more time between samples for signal pro-
cessing algorithms to do their work; that
is, lower sampling rates ease the process-
ing burden. Caution is required, though:
An input signal near twice the sampling
frequency would produce the same output
as that of Fig 16.3. To use this technique,
then, we must first limit the bandwidth
(BW) of the input: A band-pass filter
(BPF) is called for. This is known as
har-
monic sampling.
The BPF is referred to as
an
anti-aliasing
filter.
Input signals must fall between the funda-
mental (or some harmonic) of the sampling
frequency and the point half way to the next
higher harmonic. A frequency translation
will take place, but no information about the
shape of the input signal will be lost. A spec-
tral representation of harmonic sampling is
16.2
Chapter 16
Fig 16.2—Spectrum of an analog sine wave (A). The spectrum of a sampling
function (B). The spectrum of the sampled sine wave (C).
Fig 16.3—Sine wave of frequency greater than the sampling frequency (A).
Harmonically sampled sine wave (B).
is introduced in ADCs by slight variations
in the exact times of sampling. Phase noise
in the ADC’s clock source, as well as other
inaccuracies in the sampling mechanisms,
produce undesired phase modulation of
the sampled signal. Again, assuming it is
uncorrelated with the input signal, this
aperture jitter noise
will be distributed
across the entire input BW. Its amplitude
is proportional to the squares of both the
desired signal’s frequency and the RMS
time jitter in the sampling rate, and in-
versely proportional to the sampling rate
itself. With contemporary crystal-derived
clock sources, aperture jitter is usually
not a significant factor until the sampling
frequencies reach VHF; even at those fre-
quencies, the effect may be small com-
pared with quantization noise.
Over-Sampling and Sigma-Delta
ADCs
The nature of the above-mentioned noise
sources is such that if we could increase the
sampling frequency by some factor N, then
digitally filter the output back down to a
lower rate, we could improve the SNR by
almost the factor N. This is because the noise
would be spread over a larger BW; much of
the high-frequency noise would be elimi-
nated by the digital filter. This technique is
called
over-sampling.
So-called
sigma-delta
converters use
this method to achieve the best possible
dynamic range. They employ one-bit
quantizers at very high speed and digital
decimation filters (described later) to re-
duce the sampling frequency, thus im-
proving SNR. They represent the state of
the art in ADC technology. Other factors,
such as the noise figure of analog stages
inside an ADC, tend to limit the SNR of
real converters to within a few dB of that
calculated by Eq 1.
Non-Linearity in ADCs
The quantization steps of a real converter
are not perfectly spaced; conversion results
are contaminated by the inaccuracy. In gen-
eral, two types of non-linearity are charac-
terized by manufacturers:
differential
non-linearity
(DNL) and
integral non-
linearity
(INL).
DNL is the measure of the output non-
uniformity from one input step to the next.
It is expressed as the maximum error in the
output between adjacent input steps as
measured over the entire input range of the
device. The worst errors usually occur near
the middle of the scale. Since we are talk-
ing about the accuracy of the smallest steps
the converter can resolve, noisy low-order
distortion products caused by this effect
limit dynamic range. Current technology
uses correction systems to compensate for
16.3
Fig 16.4—Spectrum of a sampling function (A). Spectrum of a band of real signals
(B). Spectrum of a harmonically sampled band of real signals (C).
shown in
Fig 16.4.
It reveals the basis for the
often-misquoted
Nyquist sampling theorem:
The sampling frequency must be at least
twice the input BW to avoid aliasing. Such
aliasing would destroy information; once
incurred, nothing can remedy it.
Data Converters and Quantization
Noise
The device used to perform sampling is
called an
analog-to-digital converter
(ADC). For each sample, an ADC pro-
duces a binary number that is directly pro-
portional to the input voltage. The number
of bits in its binary output limits the num-
ber of discrete voltage levels that can be
represented. An 8-bit ADC, for example,
can only give one of 256 values. This
means the amplitude reported is not the
exact amplitude of the input, but only the
closest value of those available. The dif-
ference is called the
quantization error.
The amplitude reported by the ADC
can, therefore, be thought of as the sum of
two signals: the desired input and the
quantization error. In a perfect ADC, the
error cannot exceed ±
1
/
2
of the value of the
least-significant bit of the converter—this
is the error signal’s peak-to-peak ampli-
tude. Assuming the desired input is chang-
ing and covers a large range of quantiza-
tion levels, the error is just as likely to be
negative as positive, and just as likely to
be small as large. Hence, the error signal
is pseudo-random and appears as
quanti-
zation noise.
This noise is spread uniformly over the
entire input BW of f
s
/2. Taking this and
the maximum signal the ADC can handle
into account, the maximum signal-to-
quantization-noise ratio produced by the
ADC is:
SNR
max
6.02 b 1.76 dB
(1)
where b is the number of bits used by the
converter.
For a simple 16-bit ADC, the SNR cannot
exceed about 98 dB. The reason we wrote
that the quantization noise was pseudo-ran-
dom and not truly random is the following:
If there were a harmonic relationship be-
tween the input signal and the sampling fre-
quency, the noise might tend to concentrate
itself at discrete frequencies.
Aperture Jitter
In addition to quantization noise, noise
DSP and Software Radio Design
temperature variations that would other-
wise further degrade performance.
An ADC is considered
monotonic
if a
steady increase in the input signal always
results in an increase in the output. Device
manufacturers hold DNL to ±0.5 bits or
better so that monotonicity is maintained.
INL is a measure of an ADC’s large-
signal handling capability. To measure it,
we first inject a signal of amplitude A and
measure the output; when we inject a sig-
nal of amplitude 100A, we expect the out-
put to grow in exact proportion. INL
represents the maximum error in the out-
put between
any two
input levels. Another
way to think about this is to plot the input
against the output and see how straight the
line is. INL produces harmonic distortion
and IMD; values for typical converters are
±1 or 2 bits over the entire range.
Spurious-Free Dynamic Range and
Dithering
Spurious-free dynamic range
(SFDR) is
defined as the ratio of the largest signal
the converter can accurately handle to the
largest source of noise and distortion
caused by effects mentioned above. Quite
often, undesired components may appear
in unexpected parts of the input spectrum;
spurious responses may be found without
apparent explanation. It turns out there are
explanations, of course, but we will defer
that discussion. Suffice it to write here that
manufacturers test for SFDR and usually
specify it on their data sheets, especially
for high-speed devices.
Sometimes noise and distortion effects
conspire to add at discrete frequencies. It is
found that the addition of random noise at
the clock input helps dissipate these spuri-
ous responses. This technique is known as
dithering.
It may seem strange, but artificial
noise—usually several bits in amplitude and
high enough in frequency to be eliminated
by the decimation filter—actually reduces
quantization noise and improves perfor-
mance rather than degrading it.
Digital-to-Analog Converters:
Additional Distortion Sources
Digital-to-analog converters (DACs) per-
form the conversion of binary numbers back
into analog voltages—the reverse operation
of ADCs. They suffer from all the inadequa-
cies described earlier, as well as a few of
their own. The first unique distortion of
DACs is one of frequency response:
zero-
order sample-and-hold distortion.
Typical converters are sample-and-hold
devices: They continue to output the last
sampled value throughout the sample
period. This effect acts as a low-pass filter
having a frequency response:
sin
f
fs
f
fs
H
r
(2)
Note the classical (sin x)/x form. The
high-frequency roll-off is quite undesir-
able in many circumstances. For example,
if the output frequency is one quarter the
sampling frequency, an attenuation of
about 1 dB will occur. Correction can be
made for this, but an increase in sampling
frequency reduces the attenuation. Inter-
polation of the sampled output signal (de-
scribed later) is called for in many cases.
Settling Time and Glitch Energy
When the output of a DAC changes from
one voltage to another, it obviously can-
not do so instantaneously; a finite time is
required for the voltage to reach its new
value. This is known as the
settling time.
It is usually defined as the time required to
settle to within some number of voltage-
equivalent bits of the final value.
Glitch energy
or
glitch area
is defined as
the product of the voltage error during the
settling time and the settling time itself.
While volt-seconds are not units of energy,
it is assumed the DAC is driving some kind
of load; thus, these units can be translated
into units of energy (watt-seconds), per-
forming work on that load. The settling
mechanism is an important factor in the
production of spurious outputs in DACs.
Manufacturers usually specify the glitch
energy for their high-speed devices. It is an
especially important number for direct-
digital-synthesis (DDS) applications.
Note also that DACs produce aliases,
again repeating at intervals of f
s
. These
must usually be removed using an analog
LPF. Occasionally, a BPF may be used,
and one of the aliases taken as the desired
output. This can be a clever way of getting
an upward frequency translation under
certain conditions.
Reducing the Sampling
Frequency: Decimation
As we have seen, sampling at high rates is
beneficial because it eases the design of the
analog filters we must use to avoid aliasing.
It also reduces quantization noise and aper-
ture jitter. We have also noted that lower
sampling rates help reduce the computa-
tional burden in DSP systems. In addition,
we will discover that when it is time to digi-
tally filter some signals, making the filter’s
BW a large fraction of the sampling fre-
quency makes it easier to build sharp-skirted
filters—exactly what DSP is famous for.
Reduction of the sampling frequency is
usually called
decimation.
Decimation is
normally done by integer factors (although
it does not have to be) and is equivalent to
resampling an already-sampled signal at a
lower rate. The resampled signal has a fam-
ily of aliases, repeating at intervals of the
lower sampling frequency; we have to re-
duce the BW to less than half this lower
sampling frequency to avoid the aliasing
that would destroy information.
The process of decimation is simple:
Just throw away the unwanted samples.
To decimate by two, for example, only
every other sample is retained. A
decima-
tion filter,
operating at the higher sam-
pling rate, f
s
, reduces signal BW to less
than f
s
/4 prior to discarding the samples to
avoid aliasing. But why spend time com-
puting filter outputs that we are only go-
ing to discard? We may compute only
those we intend to keep. This is exactly
the same as running the decimation filter
at the lower rate. This method is typical of
those used by DSP designers to save time
and effort. See the chapter Appendix for a
software project (Project A) that demon-
strates decimation using Alkin’s
PC-DSP
program. This program is included with
the book listed in the
Bibliography.
Increasing the Sampling Fre-
quency: Interpolation
We learned that when it is time to con-
vert back to analog, an artificial increase
in sampling rate may be advantageous. It
will push aliases higher in frequency
where they are easier to remove by analog
filtering, and it will relieve some of the
sample-and-hold distortion. So, even hav-
ing decimated the data at some earlier
stage in our designs, we may later employ
the process of
interpolation.
Decimation was performed by deleting
samples. Interpolation is performed by
inserting them. The inserted samples have
a value of zero and are placed between the
existing samples. While this increases the
sampling frequency, the information in the
original samples is not destroyed; how-
ever, new information is added in the form
of aliases, and an
interpolation filter
is
usually required. This filter, most often a
low-pass, operates at the higher sampling
frequency, f
s
, and eliminates components
in the interpolated data above half the
original sampling frequency.
The way numbers are represented in
DSPs is a major consideration. Let’s take
a look at this before moving on to filtering
algorithms.
Representation of Numbers:
Floating-Point vs Fixed-Point
One of the things that makes general-
purpose computers so useful is their abil-
16.4
Chapter 16
ity to perform
floating-point
calculations.
In this form of numeric representation,
numbers are stored in two pieces: a frac-
tional part, or
mantissa,
and an exponent.
The mantissa is assumed to be a binary
number representing an absolute value
less than unity, and the exponent, a binary
integer. This approach allows the com-
puter to handle a large range of numbers,
from very small to very large. Some DSP
chips support floating-point calculations,
but it is not as great an advantage in signal
processing as it is in general-purpose com-
puting because the range of values we are
dealing with in DSP is limited anyway.
For this reason,
fixed-point
processors are
common in DSP.
A fixed-point processor treats numbers as
just the mantissa and does away with the
exponent. The radix point—the separation
between the integer and fractional parts of a
number—is usually assumed to reside to the
left of the most-significant bit. This is con-
venient, since the product of two fractions
less than unity is always another fraction less
than unity. The
sum
of two fractions, though,
may be greater than unity:
overflow
would
be the result. Overflow is a constant concern
for fixed-point DSP programmers and leads
to considerations for
scaling
of data, as dis-
cussed further below, which may limit sys-
tem dynamic range to less than the data
converters’ capabilities.
DSP ALGORITHMS FOR RADIO
Digital Filters
The ability to construct high-perfor-
mance filters is probably the most im-
portant rationale for using DSP in radio
transceivers. An expensive crystal or
mechanical filter having a single BW can
be replaced by a set of superior digital fil-
ters, offering as many BWs as the associ-
ated on-board memory can support.
As shape-factor requirements get more
stringent, filters get more complex. As a
filter gets more complex—with additional
inductors and capacitors in the analog case,
or additional delay elements in the digital
case—the sensitivity of the filter’s re-
sponse to errors in the element values be-
comes more severe. Thus, for analog filters,
precise values of resistance, inductance and
capacitance must be maintained if the filter
is to operate as designed. Establishing those
values is difficult; holding them within
tolerances over temperature variations and
aging is more so. DSP filters, on the other
hand, are unchanging. The “component”
values are numbers stored in a computer
that are not susceptible to temperature
changes or aging. Filters that would be
impractical or impossible in the analog
realm are easily implemented by DSP algo-
rithms.
We can build digital filters having lin-
ear phase responses, which is very diffi-
cult in the analog world. This is an
advantage mainly for digital communica-
tion modes such as FSK and PSK. Also,
filters may be combined numerically to
yield composite responses without the
need for adding hardware. This is useful
for passband tuning or graphic-equalizer
applications.
DSP filters are usually characterized by
their
impulse responses.
The impulse re-
sponse of a digital filter is the output of the
filter when the input is a one-sample,
unity-amplitude impulse. Impulse re-
sponse is directly related to frequency re-
sponse by a
Fourier transform,
about
which we will learn more later. Suffice it
to write for now that digital filters may be
broadly divided into two classes: finite
impulse response (FIR) and infinite im-
pulse response (IIR). The presence or ab-
sence of feedback separates the two.
FIR Filters
Take a look at the block diagram of the
FIR filter shown in
Fig 16.5.
The string of
boxes labeled z
-1
is simply a delay line,
with each box representing a one-sample
delay. Programmers will note that with
one input sample in each position, this is
just a buffer of length five. Each buffer
location may be referred to as a
tap
in the
delay line. The datum at each tap, x(n), is
multiplied by one of the filter
coefficients,
h(n). All the products are summed at each
sample time to produce the filter output.
At the next sample time, samples are
shifted down the delay line by one posi-
tion and the
multiply-and-accumulate
(MAC) operation is performed again. Co-
efficients remain in place and do not shift.
The mathematical expression describing
this repetitive MAC operation is also
called a
convolution sum:
y( k )
L 1
n 0
h ( n ) x( k n )
(3)
Fig 16.5—Block diagram of an FIR filter for L = 5.
DSP and Software Radio Design
16.5

Plik z chomika:

Inne pliki z tego folderu:

Inne foldery tego chomika:

Zgłoś jeśli naruszono regulamin