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FPGA Design Guide
Lattice Semiconductor Corporation
5555 NE Moore Court
Hillsboro, OR 97124
(503) 268-8000
September 16, 2008
Copyright
Copyright © 2008 Lattice Semiconductor Corporation.
This document may not, in whole or part, be copied, photocopied,
reproduced, translated, or reduced to any electronic medium or machine-
readable form without prior written consent from Lattice Semiconductor
Corporation.
Trademarks
Lattice Semiconductor Corporation, L Lattice Semiconductor Corporation
(logo), L (stylized), L (design), Lattice (design), LSC, E
2
CMOS, Extreme
Performance, FlashBAK, flexiFlash, flexiMAC, flexiPCS, FreedomChip, GAL,
GDX, Generic Array Logic, HDL Explorer, IPexpress, ISP, ispATE, ispClock,
ispDOWNLOAD, ispGAL, ispGDS, ispGDX, ispGDXV, ispGDX2,
ispGENERATOR, ispJTAG, ispLEVER, ispLeverCORE, ispLSI, ispMACH,
ispPAC, ispTRACY, ispTURBO, ispVIRTUAL MACHINE, ispVM, ispXP,
ispXPGA, ispXPLD, LatticeEC, LatticeECP, LatticeECP-DSP, LatticeECP2,
LatticeECP2M, LatticeMico8, LatticeMico32, LatticeSC, LatticeSCM,
LatticeXP, LatticeXP2, MACH, MachXO, MACO, ORCA, PAC, PAC-Designer,
PAL, Performance Analyst, PURESPEED, Reveal, Silicon Forest,
Speedlocked, Speed Locking, SuperBIG, SuperCOOL, SuperFAST,
SuperWIDE, sysCLOCK, sysCONFIG, sysDSP, sysHSI, sysI/O, sysMEM, The
Simple Machine for Complex Design, TransFR, UltraMOS, and specific
product designations are either registered trademarks or trademarks of
Lattice Semiconductor Corporation or its subsidiaries in the United States
and/or other countries. ISP, Bringing the Best Together, and More of the Best
are service marks of Lattice Semiconductor Corporation.
HyperTransport is a licensed trademark of the HyperTransport Technology
Consortium in the U.S. and other jurisdictions.
Other product names used in this publication are for identification purposes
only and may be trademarks of their respective companies.
Disclaimers
NO WARRANTIES: THE INFORMATION PROVIDED IN THIS DOCUMENT
IS “AS IS” WITHOUT ANY EXPRESS OR IMPLIED WARRANTY OF ANY
KIND INCLUDING WARRANTIES OF ACCURACY, COMPLETENESS,
MERCHANTABILITY, NONINFRINGEMENT OF INTELLECTUAL
PROPERTY, OR FITNESS FOR ANY PARTICULAR PURPOSE. IN NO
EVENT WILL LATTICE SEMICONDUCTOR CORPORATION (LSC) OR ITS
SUPPLIERS BE LIABLE FOR ANY DAMAGES WHATSOEVER (WHETHER
DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL,
INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS,
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IN THIS DOCUMENT, EVEN IF LSC HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES. BECAUSE SOME JURISDICTIONS
PROHIBIT THE EXCLUSION OR LIMITATION OF CERTAIN LIABILITY,
SOME OF THE ABOVE LIMITATIONS MAY NOT APPLY TO YOU.
LSC may make changes to these materials, specifications, or information, or
to the products described herein, at any time without notice. LSC makes no
commitment to update this documentation. LSC reserves the right to
discontinue any product or service without notice and assumes no obligation
FPGA Design Guide
ii
to correct any errors contained herein or to advise any user of this document
of any correction if such be made. LSC recommends its customers obtain the
latest version of the relevant information to establish, before ordering, that the
information being relied upon is current.
Type Conventions Used in This Document
Convention Meaning or Use
Bold
<Italic>
Ctrl+L
Courier
...
.
.
.
[ ]
Items in the user interface that you select or click. Text that you type
into the user interface.
Variables in commands, code syntax, and path names.
Press the two keys at the same time.
Code examples. Messages, reports, and prompts from the software.
Omitted material in a line of code.
Omitted lines in code and report examples.
Optional items in syntax descriptions. In bus specifications, the
brackets are required.
Grouped items in syntax descriptions.
Repeatable items in syntax descriptions.
( )
{ }
|
A choice between items in syntax descriptions.
FPGA Design Guide
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FPGA Design Guide
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Contents
Chapter 1
Chapter 2
Introduction
1
3
Moving Designs from Altera
Conversion Guidelines
3
Converting Design Constraints
4
Converting Memory Blocks
7
Converting PLL Blocks
9
Converting DDR Interfaces
11
Chapter 3
Moving Designs from Xilinx
13
Migrating Xilinx Spartan Designs to LatticeECP/EC
14
Replacing Commonly Used Xilinx Primitives
14
Replacing DCM/DLL Elements
17
Comparing Xilinx and Lattice Semiconductor Block Memory
18
Xilinx Multiplier Versus the Lattice Semiconductor DSP Block
22
Converting DDR Interfaces
23
Replacing Constraints
24
Converting Xilinx Virtex II to LatticeECP/EC Devices
27
Converting Xilinx DLL to Lattice Semiconductor PLL
27
Creating MUXCY and MUXCY_L Verilog HDL Modules
28
Wide Multiplexing
28
Optimal Carry-Chain Handling
28
Converting Xilinx RAMB16_S36_S36 to Verilog HDL
29
Converting DDR Interfaces
31
Chapter 4
Incremental and Modular Design Methods
Necessity and Benefits
33
Typical Work Flow and Data Flow
Major Advantages
35
Incremental Changes
36
Identify Design Candidates
36
34
33
FPGA Design Guide
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