Alto_aVerb_FX_Service_Manual.pdf

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Service Manual
Model:
αVERB
24x32 BIT DIGITAL EFFECTS
www.altoproaudio.com
Version: 1.1
CONTENTS
1. Specification
2. Block Diagram
3. Schematic Diagram
4. Printed Circuit Board
5. Wiring Diagram
6. Test Procedure
7. Electrical Parts List
8. Exploded Views & Mechanical Parts List
9. Notes
1. SPECIFICATION (aVERB)
Electrical
Frequency Response:
S/N Ratio (process)
S/N Ratio (bypass)
THD+Noise:
Input
Number of Channels:
Format:
Maximum Level (bypass):
Impedance:
A/D - D/A Conversions
A/D converter:
D/A converter:
Output
Number of Channels:
Format:
Maximum Level (bypass):
Output Impedance:
Front Panel
Controls
Indicators
Rear Panel
IN/OUT levels (ANALOG)
Output (LEFT, RIGHT)
BYPASS
Power
Processing and Memory
Processor Speed:
Internal DSP resolution:
Main Preset Programs
Preset Total Combinations
Internal digital audio memory:
Physical
Net Weight:
Dimension(WxDxH):
+0.5 / -1.5 dB from 20Hz to 20 kHz
80 dB "A" wtg, 20 Hz-22kHz
>90 dB "A" wtg, 20 Hz-22kHz
<0.008% @ 1kHz (0dBV, bypass)
2
1/4" unbalanced
+9 dBu
>500 Kohms
1 bit Sigma-Delta
1 bit Sigma-Delta
2
1/4" unbalanced
+9 dBu
<500 ohms
Input/Output Levels (ANALOG)
PROGRAM selections (2 knobs)
Power, Signal clip LED
1/4" 2-conductor (mono)
1/4" 2-conductor (mono)
1/4" 2-conductor (auto-sense pedal type)
for momentary footswitches
9 Volt AC Power Transformer
12 MIPs (million instructions per second)
52 bit MPY accumulator
16
256
3000 milliseconds
1kg(2.20lb)
200(mm) 150(mm) 45(mm)
(7.87" x 5.91"x 1.77")
1
4
2
3
alphaverb BLOCK DIAGRAM
D
D
AD0-AD7
DSP
POWER SUPPLY
VOLTAGE REGULATOR
( U8 TMS57002DPHA )
EA0-EA9
( U10,U11 )
MEMORY (DRAM)
ED0-ED7
MPU
AC 9V
INPUT
( U9 P87C54UBAA )
SI0
+5V
-5V
11.0592MHZ
LRCKIN=43.20KHZ
BCK=1.382MHZ
SO0
C
FOOTSWITCH
CONTROL
C
ENCODER A
PROGRAM
STEREO AUDIO CODEC
A/D and D/A CONVERTER
( U6 PCM3001E )
IN-R
IN-L OUT-R OUT-L
Q1
11.0592MHZ
CLOCK DIVIDE
( U7 74HC393 )
FOOT
SWITCH
MIX CONTROL
PJ5
ENCODER B
VARIATIONS
B
INPUT BUFFER & AMPLIFIER
OUTPUT AMPLIFIER
PJ3
B
PJ1
INPUT R
OUTPUT R
INPUT LEVEL
OUTPUT LEVEL
PJ2
PJ4
INPUT L
(MONO INPUT)
INPUT LEVEL
OUTPUT LEVEL
OUTPUT L
A
A
1
2
3
4
1
2
3
4
5
6
7
8
INPUTL
10
+5V
11
5
6
INPUTR
+5V
D
U5
PCM3001E
U11E
74HC04D
RS-CODEC
C95 100nF
DGND
BCK
CLK
MR
DGND
2
DGND
1
3
4
5
6
Q0
Q1
Q2
Q3
DGND
U11C
74HC04D
D
C38 10uF
U6A
74HC393D
12
13
9
8
C37
10uF
C35 C36
470P
U11F
74HC04D
U11D
74HC04D
R17
4K7
CLK-Q3
DGND
13
CLK
12
1
MR
DGND
LRCKIN
DGND
Q0
Q1
Q2
Q3
470P
Q1
11.0592MHz
ENCODERA4
+5V
R28
4K7
C34
10uF
C32
22P
DGND
SO0
SI0
SO0
BCK
LRCKIN
C39
100nF
C33
22P
U6B
74HC393D
11
10
9
8
ENCODERA3
R27
4K7
C30
1uF
OUTPUTR
AGND
DGND
C40
100nF
VOUTL
DGND
ENCODERA2
1
2
3
4
5
6
7
8
9
10
11
VOUTR
12
13
14
VINL
VCC1
AGND1
VREFL
VREFR
VINR
CINPR
CINNR
CINLN
CINPL
VCOM
VOUTR
AGND2
VCC2
RSTB
FMT0
FMT1
FMT2
DGND
VDD
CLKIO
XTO
XTI
DOUT
DIN
BCKIN
LRCIN
VOUTL
28
27
26
25
24
23
22
21
20
19
18
17
16
15
R26
4K7
OUTPUTL
C41
100nF
C45
82P
U11A
74HC04D
+5V
2
SI0
SI1
1
2
3
4
5
6
D3
D2
COM
COM
D1
D0
AGND
ENCODERA1
DGND
R25
4K7
LRCKIN
ENCA
288S0121
R30
100K
R18
100R
R29
100K
C31
1uF
+5V
DGND
C
STRB
CLOAD
PLOAD
BCKI
ED0
ED1
+5V
CS
R/W
PLOAD
DREADY
CLOAD
STRB
NC
VCC
VSS
NC
BCKI
LRCKI
NC
SI0
SI1
SYNC
C
C27
47uF/25V
DGND
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
R31
100R
EA9
EA0
EA1
EA2
EA3
+5V
SO0
SO1
9
10
11
12
13
1
2
3
4
5
I/00
I/01
WE
RAS
A9
A0
A1
A2
A3
+5V
U9
GM71C4256BJ60
ED4
ED5
DGND
I/03
I/02
CAS
OE
A8
A7
A6
A5
A4
26
25
ED3
24
ED2
23
22
18
17
16
15
14
U10
GM71C4256BJ60
JP2
2P-2.5
MUTE
EMPTY
RS
OVM
BIO
+5V
+5V
EA9
EA8
EA7
EA6
EA5
EA4
EA0
EA1
EA2
EA3
1
2
3
4
5
9
10
11
12
13
I/00
I/01
WE
RAS
A9
A0
A1
A2
A3
+5V
DGND
I/03
I/02
CAS
OE
A8
A7
A6
A5
A4
26
25
ED7
24
ED6
23
22
18
17
16
15
14
RST
D4
1N4148
CAS
10
22
9
8
7
6
5
4
3
2
1
R24
100K
C29
1uF
AD7
AD6
C28
100nF
U7
TMS57002
DGND
RST
VSS
P 1.7
P 1.6
P 1.5
P 1.4
P 1.3
P 1.2
P 1.1
P 1.0
NC
DGND
DGND
U8
P87C54UBAA
(AlphaComp:P87C52UBAA)
EA8
EA7
EA6
EA5
EA4
C97
100nF
WE
3
4
DGND
DGND
C96
100nF
AD5
AD4
AD3
AD2
AD1
AD0
EA9
EA8
TEST2
TEST1
TEST0
EA7
NC
EA6
EA5
VCC
VSS
EA4
EA3
NC
EA2
NC
EA1
EA0
DGND
DGND
B
R37
10K
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
ED7
ED6
ED5
ED4
ED3
ED2
ED1
ED0
F11.0592M
44
43
42
41
40
39
38
37
36
20
21
VDD
P 0.0/AD0
P 0.1/AD1
P 0.2/AD2
P 0.3/AD3
P 0.4/AD4
P 0.5/AD5
P 0.6/AD6
P 0.7/AD7
XTAL2
XTAL1
P 2.0/A8
P 2.1/A9
P 2.2/A10
P 2.3/A11
P 2.4/A12
P 2.5/A13
P 2.6/A14
P 2.7/A15
NC
EA/VPP
NC
24
25
26
27
28
29
30
31
23
35
34
A15
WE
Analog Stage & Power supply
a-verbIO.SCH
U11B
74HC04D
INPUTR
INPUTL
OUTPUTR
OUTPUTL
INPUTR
INPUTL
OUTPUTR
OUTPUTL
RXD/P3.0
TXD/P3.1
INT0/P3.2
INT1/P3.3
T0/P3.4
T1/P3.5
WR/P3.6
RD/P3.7
NC
PSEN
ALE
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
MUTE
EMPTY
NC
NC
RS
OVFM
OVFA
BIO
PC0
D7
D6
VCC
VCC
D5
D4
NC
D3
D2
D1
D0
NC
NC
EA9
EA8
SYPOL
BCK0
NC
NC
LRCK0
S00
S01
CAS
RAS
CLKSEL
CLKIN
VSS
VSS
WE
ED7
ED6
ED5
ED4
ED3
ED2
NC
NC
ED1
ED0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
LINK
LINK.SCH
B
R36
10K
+5V
11
13
14
15
16
17
18
19
12
32
33
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
EA7
EA6
EA5
EA4
EA3
EA2
14
R40 0R0
+VCC
+5V
ENCODERB4
+5V
R39 0R0
R38 0R0
R2
10K
R1
220R
Footswitch live
+5V
DGND
R35
4K7
DL1
RED
R44
470R
1/4W
(OVER-LOAD)
C42
100nF
ENCODERB3
PJ5
LJB0661-6
R3
1K
L9
BLM21A102
74HC04D
7
U11G
14
Footswitch live
RS-CODEC
EA1
EA0
+5V
+5V
U6C
C98
74HC393D
100nF
7
C99
100nF
R34
4K7
DL2
RED
C43
100nF
ENCODERB2
A
R33
4K7
C44
100nF
1
2
3
4
5
6
D3
D2
COM
COM
D1
D0
ENCODERB1
DGND
DGND
R32
4K7
ENCB
288S0121
OVM
(PWR ON)
2
22
33
3
11
1
DGND
DGND
DGND
DGND
A
C7
100nF
DGND
FSP
AGND2
Title
Size
A3
Date:
File:
MODEL:ALTO AlphaVERB
Number
A-VERBMAIN.SCH
8-Jan-2002
Sheet of
D:\shung\PC27\ALTO\Digital\AlfaVerb\SCHPCB\alphaverb.ddb
Drawn By:
4
5
6
7
Revision
2002/01/06
KEVIN LIN.
8
1
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